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stm32: Support setting the stm32f0 internal clock trim value 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2021-01-18 12:47:59 -05:00
parent 611b76369f
commit 28bca7da77
2 changed files with 11 additions and 1 deletions
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9
src/stm32/Kconfig
View File

@ -187,6 +187,15 @@ choice
bool "Pins PB12(rx) and PB13(tx)" if MACH_STM32F4
endchoice
config STM32F0_TRIM
int "Internal clock trim override" if LOW_LEVEL_OPTIONS && MACH_STM32F0 && STM32_CLOCK_REF_INTERNAL && !USBSERIAL
default 16
help
Specify the internal clock trim value. Setting this can be
useful if the factory default internal clock is not accurate.
Default is 16 (use factory default). Each increment increases
the clock rate by ~240KHz.
config STM32F042_PIN_SWAP
bool "Use PA9/PA10 for USB or CAN" if MACH_STM32F042
depends on (USBSERIAL || CANSERIAL) && MACH_STM32F042

3
src/stm32/stm32f0.c
View File

@ -127,7 +127,8 @@ pll_setup(void)
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 48Mhz PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ;
RCC->CR |= RCC_CR_HSEON;
RCC->CR = ((RCC->CR & ~RCC_CR_HSITRIM) | RCC_CR_HSEON
| (CONFIG_STM32F0_TRIM << RCC_CR_HSITRIM_Pos));
cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((div - 2) << RCC_CFGR_PLLMUL_Pos);
} else {
// Configure 48Mhz PLL from internal 8Mhz oscillator (HSI)