mirror of https://github.com/Desuuuu/klipper.git
1082 lines
44 KiB
C
1082 lines
44 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_ll_fsmc.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief Header file of FSMC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_LL_FSMC_H
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#define __STM32F1xx_LL_FSMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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#if defined(FSMC_BANK1)
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/** @addtogroup FSMC_LL
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* @{
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*/
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/* Exported typedef ----------------------------------------------------------*/
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/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
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* @{
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*/
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/**
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* @brief FSMC NORSRAM Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
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This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
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multiplexed on the data bus or not.
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This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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uint32_t MemoryType; /*!< Specifies the type of external memory attached to
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the corresponding memory device.
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This parameter can be a value of @ref FSMC_Memory_Type */
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uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
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uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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memory, valid only when accessing Flash memories in burst mode.
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This parameter can be a value of @ref FSMC_Wrap_Mode */
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uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Timing */
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uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
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This parameter can be a value of @ref FSMC_Write_Operation */
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uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal */
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uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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This parameter can be a value of @ref FSMC_Extended_Mode */
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uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref FSMC_AsynchronousWait */
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uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
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This parameter can be a value of @ref FSMC_Write_Burst */
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}FSMC_NORSRAM_InitTypeDef;
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/**
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* @brief FSMC NORSRAM Timing parameters structure definition
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*/
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typedef struct
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{
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uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 255.
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@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
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NOR Flash memories. */
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uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is only used for multiplexed NOR Flash memories. */
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uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
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HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
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@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
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accesses. */
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uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The parameter value depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
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with synchronous burst mode enable */
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uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
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This parameter can be a value of @ref FSMC_Access_Mode */
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}FSMC_NORSRAM_TimingTypeDef;
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#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
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/**
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* @brief FSMC NAND Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
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This parameter can be a value of @ref FSMC_NAND_Bank */
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uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
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This parameter can be any value of @ref FSMC_Wait_feature */
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uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be any value of @ref FSMC_NAND_Data_Width */
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uint32_t EccComputation; /*!< Enables or disables the ECC computation.
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This parameter can be any value of @ref FSMC_ECC */
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uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
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This parameter can be any value of @ref FSMC_ECC_Page_Size */
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uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_NAND_InitTypeDef;
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/**
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* @brief FSMC NAND/PCCARD Timing parameters structure definition
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*/
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typedef struct
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{
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uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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the command assertion for NAND-Flash read or write access
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to common/Attribute or I/O memory space (depending on
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the memory space timing to be configured).
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
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command for NAND-Flash read or write access to
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common/Attribute or I/O memory space (depending on the
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memory space timing to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
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(and data for write access) after the command de-assertion
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for NAND-Flash read or write access to common/Attribute
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or I/O memory space (depending on the memory space timing
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to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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data bus is kept in HiZ after the start of a NAND-Flash
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write access to common/Attribute or I/O memory space (depending
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on the memory space timing to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_NAND_PCC_TimingTypeDef;
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/**
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* @brief FSMC NAND Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
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This parameter can be any value of @ref FSMC_Wait_feature */
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uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_PCCARD_InitTypeDef;
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#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
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* @{
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*/
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/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
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* @{
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*/
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/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
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* @{
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*/
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#define FSMC_NORSRAM_BANK1 0x00000000U
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#define FSMC_NORSRAM_BANK2 0x00000002U
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#define FSMC_NORSRAM_BANK3 0x00000004U
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#define FSMC_NORSRAM_BANK4 0x00000006U
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
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* @{
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*/
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#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
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#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
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/**
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* @}
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*/
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/** @defgroup FSMC_Memory_Type FSMC Memory Type
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* @{
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*/
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#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
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#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
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#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
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/**
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* @}
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*/
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/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
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* @{
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*/
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
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/**
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* @}
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*/
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/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
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* @{
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*/
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#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
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#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
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/**
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* @}
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*/
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/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
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* @{
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*/
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#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
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#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
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* @{
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*/
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#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
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#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
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/**
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* @}
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*/
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/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
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* @{
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*/
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#define FSMC_WRAP_MODE_DISABLE 0x00000000U
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#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
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* @{
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*/
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#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
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#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Operation FSMC Write Operation
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* @{
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*/
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#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
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#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
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* @{
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*/
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#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
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#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
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/**
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* @}
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*/
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/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
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* @{
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*/
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#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
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#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
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/**
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* @}
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*/
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/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
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* @{
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*/
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#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
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#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Burst FSMC Write Burst
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* @{
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*/
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#define FSMC_WRITE_BURST_DISABLE 0x00000000U
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#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
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/**
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* @}
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*/
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/** @defgroup FSMC_Access_Mode FSMC Access Mode
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* @{
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*/
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#define FSMC_ACCESS_MODE_A 0x00000000U
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#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
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#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
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#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
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/**
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* @}
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*/
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/**
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* @}
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*/
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#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
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/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
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* @{
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*/
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/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
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* @{
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*/
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#define FSMC_NAND_BANK2 0x00000010U
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#define FSMC_NAND_BANK3 0x00000100U
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_feature FSMC Wait feature
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* @{
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*/
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#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
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#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
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/**
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* @}
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*/
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/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
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* @{
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*/
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#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
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#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP)
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/**
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* @}
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*/
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/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
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* @{
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*/
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#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
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#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0)
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/**
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* @}
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*/
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/** @defgroup FSMC_ECC FSMC NAND ECC
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* @{
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*/
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#define FSMC_NAND_ECC_DISABLE 0x00000000U
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#define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN)
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/**
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* @}
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*/
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/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
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* @{
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*/
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#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
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#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0)
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#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1)
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#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
|
|
|
/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
|
|
* @brief FSMC Interrupt definition
|
|
* @{
|
|
*/
|
|
#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
|
|
#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
|
|
#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
|
|
* @brief FSMC Flag definition
|
|
* @{
|
|
*/
|
|
#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
|
|
#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
|
|
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
|
|
#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
|
|
* @{
|
|
*/
|
|
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
|
|
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
|
|
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
|
|
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
|
|
|
|
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
|
|
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
|
|
#define FSMC_NAND_DEVICE FSMC_Bank2_3
|
|
#define FSMC_PCCARD_DEVICE FSMC_Bank4
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
|
|
* @brief macros to handle NOR device enable/disable and read/write operations
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NORSRAM device access.
|
|
* @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
* @param __BANK__: FSMC_NORSRAM Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
|
|
|
|
/**
|
|
* @brief Disable the NORSRAM device access.
|
|
* @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
* @param __BANK__: FSMC_NORSRAM Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
|
|
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
|
|
* @brief macros to handle NAND device enable/disable
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NAND device access.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
|
|
SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
|
|
|
|
/**
|
|
* @brief Disable the NAND device access.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
|
|
CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
|
|
* @brief macros to handle PCCARD read/write operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enable the PCCARD device access.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
|
|
|
|
/**
|
|
* @brief Disable the PCCARD device access.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
|
|
* @brief macros to handle FSMC flags and interrupts
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NAND device interrupt.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __INTERRUPT__: FSMC_NAND interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
|
|
SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Disable the NAND device interrupt.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __INTERRUPT__: FSMC_NAND interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
|
|
CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Get flag status of the NAND device.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__ : FSMC_NAND Bank
|
|
* @param __FLAG__ : FSMC_NAND flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval The state of FLAG (SET or RESET).
|
|
*/
|
|
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
|
|
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
|
/**
|
|
* @brief Clear flag status of the NAND device.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __FLAG__: FSMC_NAND flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
|
|
CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
|
|
|
|
/**
|
|
* @brief Enable the PCCARD device interrupt.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __INTERRUPT__: FSMC_PCCARD interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the PCCARD device interrupt.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __INTERRUPT__: FSMC_PCCARD interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Get flag status of the PCCARD device.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __FLAG__: FSMC_PCCARD flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval The state of FLAG (SET or RESET).
|
|
*/
|
|
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
|
|
|
/**
|
|
* @brief Clear flag status of the PCCARD device.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __FLAG__: FSMC_PCCARD flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
|
|
((__BANK__) == FSMC_NORSRAM_BANK2) || \
|
|
((__BANK__) == FSMC_NORSRAM_BANK3) || \
|
|
((__BANK__) == FSMC_NORSRAM_BANK4))
|
|
|
|
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
|
|
((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
|
|
|
|
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
|
|
((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
|
|
((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
|
|
|
|
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
|
|
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
|
|
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
|
|
|
|
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
|
|
((__BURST__) == FSMC_WRITE_BURST_ENABLE))
|
|
|
|
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
|
|
((__MODE__) == FSMC_ACCESS_MODE_B) || \
|
|
((__MODE__) == FSMC_ACCESS_MODE_C) || \
|
|
((__MODE__) == FSMC_ACCESS_MODE_D))
|
|
|
|
#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
|
|
((__BANK__) == FSMC_NAND_BANK3))
|
|
|
|
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
|
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
|
|
|
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
|
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
|
|
|
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
|
|
((__STATE__) == FSMC_NAND_ECC_ENABLE))
|
|
|
|
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
|
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
|
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
|
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
|
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
|
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
|
|
|
/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
|
|
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
|
|
|
|
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
|
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
|
|
|
|
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
|
|
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
|
|
|
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
|
|
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
|
|
|
|
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
|
|
((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
|
|
|
|
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
|
|
((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
|
|
|
|
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
|
|
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
|
|
|
|
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
|
|
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
|
|
|
|
#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
|
|
|
|
/** @defgroup FSMC_Data_Latency FSMC Data Latency
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
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/**
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* @}
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*/
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/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
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* @{
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*/
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#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
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/**
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* @}
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*/
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/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
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* @{
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*/
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#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
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* @{
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*/
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#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
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/**
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* @}
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*/
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/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
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* @{
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*/
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#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
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* @{
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*/
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/* ----------------------- FSMC registers bit mask --------------------------- */
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#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
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/* --- PCR Register ---*/
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/* PCR register clear mask */
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#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \
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FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \
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FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \
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FSMC_PCRx_TAR | FSMC_PCRx_ECCPS))
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|
|
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/* --- PMEM Register ---*/
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/* PMEM register clear mask */
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|
#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\
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FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
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|
|
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/* --- PATT Register ---*/
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|
/* PATT register clear mask */
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|
#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\
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FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
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|
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#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
|
/* --- BCR Register ---*/
|
|
/* BCR register clear mask */
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|
#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \
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FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \
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|
FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \
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|
FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
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|
FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \
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|
FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \
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|
FSMC_BCRx_CBURSTRW))
|
|
/* --- BTR Register ---*/
|
|
/* BTR register clear mask */
|
|
#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
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|
FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
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|
FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
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|
FSMC_BTRx_ACCMOD))
|
|
|
|
/* --- BWTR Register ---*/
|
|
/* BWTR register clear mask */
|
|
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
|
|
#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
|
|
FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
|
|
FSMC_BWTRx_BUSTURN))
|
|
#else
|
|
#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
|
|
FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
|
|
FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
|
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
|
|
|
/* --- PIO4 Register ---*/
|
|
/* PIO4 register clear mask */
|
|
#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
|
|
FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
|
|
/**
|
|
* @}
|
|
*/
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
/** @addtogroup FSMC_LL_Exported_Functions
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup FSMC_NORSRAM
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup FSMC_NORSRAM_Group1
|
|
* @{
|
|
*/
|
|
/* FSMC_NORSRAM Controller functions ******************************************/
|
|
/* Initialization/de-initialization functions */
|
|
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
|
|
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
|
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup FSMC_NORSRAM_Group2
|
|
* @{
|
|
*/
|
|
/* FSMC_NORSRAM Control functions */
|
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
|
|
/** @addtogroup FSMC_NAND
|
|
* @{
|
|
*/
|
|
|
|
/* FSMC_NAND Controller functions **********************************************/
|
|
/* Initialization/de-initialization functions */
|
|
/** @addtogroup FSMC_NAND_Exported_Functions_Group1
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
|
|
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* FSMC_NAND Control functions */
|
|
/** @addtogroup FSMC_NAND_Exported_Functions_Group2
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
|
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup FSMC_PCCARD
|
|
* @{
|
|
*/
|
|
|
|
/* FSMC_PCCARD Controller functions ********************************************/
|
|
/* Initialization/de-initialization functions */
|
|
/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
|
|
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
|
|
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* FSMC_BANK1 */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F1xx_LL_FSMC_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|