mirror of https://github.com/Desuuuu/klipper.git
115 lines
10 KiB
C
115 lines
10 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_MATRIX_INSTANCE_
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#define _SAM4E_MATRIX_INSTANCE_
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/* ========== Register definition for MATRIX peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
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#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
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#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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#define REG_MATRIX_PRBS0 (0x400E0284U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
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#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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#define REG_MATRIX_PRBS1 (0x400E028CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
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#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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#define REG_MATRIX_PRBS2 (0x400E0294U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
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#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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#define REG_MATRIX_PRBS3 (0x400E029CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
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#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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#define REG_MATRIX_PRBS4 (0x400E02A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
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#define REG_MATRIX_PRAS5 (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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#define REG_MATRIX_PRBS5 (0x400E02ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
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#define REG_MATRIX_PRAS6 (0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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#define REG_MATRIX_PRBS6 (0x400E02B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
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#define REG_MATRIX_PRAS7 (0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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#define REG_MATRIX_PRBS7 (0x400E02BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
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#define REG_MATRIX_PRAS8 (0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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#define REG_MATRIX_PRBS8 (0x400E02C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
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#define REG_MATRIX_PRAS9 (0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
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#define REG_MATRIX_PRBS9 (0x400E02CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
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#define REG_MATRIX_PRAS10 (0x400E02D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
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#define REG_MATRIX_PRBS10 (0x400E02D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
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#define REG_MATRIX_PRAS11 (0x400E02D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
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#define REG_MATRIX_PRBS11 (0x400E02DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
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#define REG_MATRIX_PRAS12 (0x400E02E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
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#define REG_MATRIX_PRBS12 (0x400E02E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
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#define REG_MATRIX_PRAS13 (0x400E02E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
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#define REG_MATRIX_PRBS13 (0x400E02ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
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#define REG_MATRIX_PRAS14 (0x400E02F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
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#define REG_MATRIX_PRBS14 (0x400E02F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
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#define REG_MATRIX_PRAS15 (0x400E02F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
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#define REG_MATRIX_PRBS15 (0x400E02FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
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#define REG_MATRIX_MRCR (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
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#define REG_MATRIX_SFR (0x400E0310U) /**< \brief (MATRIX) Special Function Register */
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#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
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#else
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#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
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#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
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#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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#define REG_MATRIX_PRBS0 (*(RwReg*)0x400E0284U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
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#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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#define REG_MATRIX_PRBS1 (*(RwReg*)0x400E028CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
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#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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#define REG_MATRIX_PRBS2 (*(RwReg*)0x400E0294U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
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#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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#define REG_MATRIX_PRBS3 (*(RwReg*)0x400E029CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
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#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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#define REG_MATRIX_PRBS4 (*(RwReg*)0x400E02A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
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#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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#define REG_MATRIX_PRBS5 (*(RwReg*)0x400E02ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
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#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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#define REG_MATRIX_PRBS6 (*(RwReg*)0x400E02B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
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#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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#define REG_MATRIX_PRBS7 (*(RwReg*)0x400E02BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
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#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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#define REG_MATRIX_PRBS8 (*(RwReg*)0x400E02C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
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#define REG_MATRIX_PRAS9 (*(RwReg*)0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
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#define REG_MATRIX_PRBS9 (*(RwReg*)0x400E02CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
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#define REG_MATRIX_PRAS10 (*(RwReg*)0x400E02D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
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#define REG_MATRIX_PRBS10 (*(RwReg*)0x400E02D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
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#define REG_MATRIX_PRAS11 (*(RwReg*)0x400E02D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
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#define REG_MATRIX_PRBS11 (*(RwReg*)0x400E02DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
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#define REG_MATRIX_PRAS12 (*(RwReg*)0x400E02E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
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#define REG_MATRIX_PRBS12 (*(RwReg*)0x400E02E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
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#define REG_MATRIX_PRAS13 (*(RwReg*)0x400E02E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
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#define REG_MATRIX_PRBS13 (*(RwReg*)0x400E02ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
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#define REG_MATRIX_PRAS14 (*(RwReg*)0x400E02F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
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#define REG_MATRIX_PRBS14 (*(RwReg*)0x400E02F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
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#define REG_MATRIX_PRAS15 (*(RwReg*)0x400E02F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
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#define REG_MATRIX_PRBS15 (*(RwReg*)0x400E02FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
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#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
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#define REG_MATRIX_SFR (*(RwReg*)0x400E0310U) /**< \brief (MATRIX) Special Function Register */
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#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_MATRIX_INSTANCE_ */
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