mirror of https://github.com/Desuuuu/klipper.git
130 lines
9.7 KiB
C
130 lines
9.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for SERCOM5
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_SERCOM5_INSTANCE_
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#define _SAMD21_SERCOM5_INSTANCE_
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/* ========== Register definition for SERCOM5 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SERCOM5_I2CM_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */
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#define REG_SERCOM5_I2CM_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */
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#define REG_SERCOM5_I2CM_BAUD (0x42001C0C) /**< \brief (SERCOM5) I2CM Baud Rate */
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#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
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#define REG_SERCOM5_I2CM_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
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#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CM_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CM Status */
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#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CM Syncbusy */
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#define REG_SERCOM5_I2CM_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CM Address */
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#define REG_SERCOM5_I2CM_DATA (0x42001C28) /**< \brief (SERCOM5) I2CM Data */
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#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) I2CM Debug Control */
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#define REG_SERCOM5_I2CS_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */
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#define REG_SERCOM5_I2CS_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */
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#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
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#define REG_SERCOM5_I2CS_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
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#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CS_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CS Status */
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#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CS Syncbusy */
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#define REG_SERCOM5_I2CS_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CS Address */
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#define REG_SERCOM5_I2CS_DATA (0x42001C28) /**< \brief (SERCOM5) I2CS Data */
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#define REG_SERCOM5_SPI_CTRLA (0x42001C00) /**< \brief (SERCOM5) SPI Control A */
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#define REG_SERCOM5_SPI_CTRLB (0x42001C04) /**< \brief (SERCOM5) SPI Control B */
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#define REG_SERCOM5_SPI_BAUD (0x42001C0C) /**< \brief (SERCOM5) SPI Baud Rate */
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#define REG_SERCOM5_SPI_INTENCLR (0x42001C14) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
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#define REG_SERCOM5_SPI_INTENSET (0x42001C16) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
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#define REG_SERCOM5_SPI_INTFLAG (0x42001C18) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM5_SPI_STATUS (0x42001C1A) /**< \brief (SERCOM5) SPI Status */
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#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) SPI Syncbusy */
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#define REG_SERCOM5_SPI_ADDR (0x42001C24) /**< \brief (SERCOM5) SPI Address */
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#define REG_SERCOM5_SPI_DATA (0x42001C28) /**< \brief (SERCOM5) SPI Data */
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#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) SPI Debug Control */
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#define REG_SERCOM5_USART_CTRLA (0x42001C00) /**< \brief (SERCOM5) USART Control A */
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#define REG_SERCOM5_USART_CTRLB (0x42001C04) /**< \brief (SERCOM5) USART Control B */
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#define REG_SERCOM5_USART_BAUD (0x42001C0C) /**< \brief (SERCOM5) USART Baud Rate */
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#define REG_SERCOM5_USART_RXPL (0x42001C0E) /**< \brief (SERCOM5) USART Receive Pulse Length */
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#define REG_SERCOM5_USART_INTENCLR (0x42001C14) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
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#define REG_SERCOM5_USART_INTENSET (0x42001C16) /**< \brief (SERCOM5) USART Interrupt Enable Set */
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#define REG_SERCOM5_USART_INTFLAG (0x42001C18) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM5_USART_STATUS (0x42001C1A) /**< \brief (SERCOM5) USART Status */
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#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) USART Syncbusy */
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#define REG_SERCOM5_USART_DATA (0x42001C28) /**< \brief (SERCOM5) USART Data */
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#define REG_SERCOM5_USART_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) USART Debug Control */
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#else
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#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */
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#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */
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#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
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#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
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#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
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#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CM Status */
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#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CM Syncbusy */
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#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CM Address */
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#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */
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#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Control */
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#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */
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#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */
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#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
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#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
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#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CS Status */
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#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CS Syncbusy */
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#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CS Address */
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#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */
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#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */
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#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */
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#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */
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#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
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#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
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#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) SPI Status */
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#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) SPI Syncbusy */
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#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) SPI Address */
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#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28UL) /**< \brief (SERCOM5) SPI Data */
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#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) SPI Debug Control */
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#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */
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#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */
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#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CUL) /**< \brief (SERCOM5) USART Baud Rate */
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#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
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#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
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#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
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#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) USART Status */
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#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) USART Syncbusy */
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#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28UL) /**< \brief (SERCOM5) USART Data */
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#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) USART Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for SERCOM5 peripheral ========== */
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#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
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#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
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#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
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#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
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#define SERCOM5_INT_MSB 6
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#endif /* _SAMD21_SERCOM5_INSTANCE_ */
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