mirror of https://github.com/Desuuuu/klipper.git
104 lines
7.1 KiB
C
104 lines
7.1 KiB
C
/**
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* \file
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*
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* \brief Instance description for RTC
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_RTC_INSTANCE_
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#define _SAMD21_RTC_INSTANCE_
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/* ========== Register definition for RTC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_RTC_READREQ (0x40001402) /**< \brief (RTC) Read Request */
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#define REG_RTC_STATUS (0x4000140A) /**< \brief (RTC) Status */
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#define REG_RTC_DBGCTRL (0x4000140B) /**< \brief (RTC) Debug Control */
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#define REG_RTC_FREQCORR (0x4000140C) /**< \brief (RTC) Frequency Correction */
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#define REG_RTC_MODE0_CTRL (0x40001400) /**< \brief (RTC) MODE0 Control */
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#define REG_RTC_MODE0_EVCTRL (0x40001404) /**< \brief (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_COUNT (0x40001410) /**< \brief (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP0 (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE1_CTRL (0x40001400) /**< \brief (RTC) MODE1 Control */
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#define REG_RTC_MODE1_EVCTRL (0x40001404) /**< \brief (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_COUNT (0x40001410) /**< \brief (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (0x40001414) /**< \brief (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP0 (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE2_CTRL (0x40001400) /**< \brief (RTC) MODE2 Control */
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#define REG_RTC_MODE2_EVCTRL (0x40001404) /**< \brief (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_CLOCK (0x40001410) /**< \brief (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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#else
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#define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */
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#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */
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#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */
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#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */
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#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */
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#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */
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#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */
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#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for RTC peripheral ========== */
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#define RTC_ALARM_NUM 1 // Number of Alarms
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#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
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#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
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#define RTC_GCLK_ID 4 // Index of Generic Clock
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#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
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#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
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#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
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#endif /* _SAMD21_RTC_INSTANCE_ */
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