mirror of https://github.com/Desuuuu/klipper.git
182 lines
14 KiB
C
182 lines
14 KiB
C
/**
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* \file
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*
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* \brief Instance description for SERCOM0
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_SERCOM0_INSTANCE_
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#define _SAMD51_SERCOM0_INSTANCE_
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/* ========== Register definition for SERCOM0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SERCOM0_I2CM_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CM Control A */
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#define REG_SERCOM0_I2CM_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CM Control B */
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#define REG_SERCOM0_I2CM_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CM Control C */
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#define REG_SERCOM0_I2CM_BAUD (0x4000300C) /**< \brief (SERCOM0) I2CM Baud Rate */
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#define REG_SERCOM0_I2CM_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
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#define REG_SERCOM0_I2CM_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
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#define REG_SERCOM0_I2CM_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM0_I2CM_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CM Status */
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#define REG_SERCOM0_I2CM_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
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#define REG_SERCOM0_I2CM_ADDR (0x40003024) /**< \brief (SERCOM0) I2CM Address */
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#define REG_SERCOM0_I2CM_DATA (0x40003028) /**< \brief (SERCOM0) I2CM Data */
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#define REG_SERCOM0_I2CM_DBGCTRL (0x40003030) /**< \brief (SERCOM0) I2CM Debug Control */
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#define REG_SERCOM0_I2CS_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CS Control A */
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#define REG_SERCOM0_I2CS_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CS Control B */
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#define REG_SERCOM0_I2CS_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CS Control C */
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#define REG_SERCOM0_I2CS_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
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#define REG_SERCOM0_I2CS_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
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#define REG_SERCOM0_I2CS_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM0_I2CS_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CS Status */
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#define REG_SERCOM0_I2CS_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
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#define REG_SERCOM0_I2CS_LENGTH (0x40003022) /**< \brief (SERCOM0) I2CS Length */
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#define REG_SERCOM0_I2CS_ADDR (0x40003024) /**< \brief (SERCOM0) I2CS Address */
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#define REG_SERCOM0_I2CS_DATA (0x40003028) /**< \brief (SERCOM0) I2CS Data */
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#define REG_SERCOM0_SPI_CTRLA (0x40003000) /**< \brief (SERCOM0) SPI Control A */
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#define REG_SERCOM0_SPI_CTRLB (0x40003004) /**< \brief (SERCOM0) SPI Control B */
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#define REG_SERCOM0_SPI_CTRLC (0x40003008) /**< \brief (SERCOM0) SPI Control C */
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#define REG_SERCOM0_SPI_BAUD (0x4000300C) /**< \brief (SERCOM0) SPI Baud Rate */
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#define REG_SERCOM0_SPI_INTENCLR (0x40003014) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
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#define REG_SERCOM0_SPI_INTENSET (0x40003016) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
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#define REG_SERCOM0_SPI_INTFLAG (0x40003018) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM0_SPI_STATUS (0x4000301A) /**< \brief (SERCOM0) SPI Status */
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#define REG_SERCOM0_SPI_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) SPI Synchronization Busy */
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#define REG_SERCOM0_SPI_LENGTH (0x40003022) /**< \brief (SERCOM0) SPI Length */
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#define REG_SERCOM0_SPI_ADDR (0x40003024) /**< \brief (SERCOM0) SPI Address */
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#define REG_SERCOM0_SPI_DATA (0x40003028) /**< \brief (SERCOM0) SPI Data */
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#define REG_SERCOM0_SPI_DBGCTRL (0x40003030) /**< \brief (SERCOM0) SPI Debug Control */
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#define REG_SERCOM0_USART_CTRLA (0x40003000) /**< \brief (SERCOM0) USART Control A */
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#define REG_SERCOM0_USART_CTRLB (0x40003004) /**< \brief (SERCOM0) USART Control B */
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#define REG_SERCOM0_USART_CTRLC (0x40003008) /**< \brief (SERCOM0) USART Control C */
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#define REG_SERCOM0_USART_BAUD (0x4000300C) /**< \brief (SERCOM0) USART Baud Rate */
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#define REG_SERCOM0_USART_RXPL (0x4000300E) /**< \brief (SERCOM0) USART Receive Pulse Length */
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#define REG_SERCOM0_USART_INTENCLR (0x40003014) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
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#define REG_SERCOM0_USART_INTENSET (0x40003016) /**< \brief (SERCOM0) USART Interrupt Enable Set */
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#define REG_SERCOM0_USART_INTFLAG (0x40003018) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM0_USART_STATUS (0x4000301A) /**< \brief (SERCOM0) USART Status */
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#define REG_SERCOM0_USART_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) USART Synchronization Busy */
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#define REG_SERCOM0_USART_RXERRCNT (0x40003020) /**< \brief (SERCOM0) USART Receive Error Count */
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#define REG_SERCOM0_USART_LENGTH (0x40003022) /**< \brief (SERCOM0) USART Length */
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#define REG_SERCOM0_USART_DATA (0x40003028) /**< \brief (SERCOM0) USART Data */
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#define REG_SERCOM0_USART_DBGCTRL (0x40003030) /**< \brief (SERCOM0) USART Debug Control */
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#else
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#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CM Control A */
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#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CM Control B */
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#define REG_SERCOM0_I2CM_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CM Control C */
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#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4000300CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
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#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
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#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
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#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
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#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CM Status */
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#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
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#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CM Address */
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#define REG_SERCOM0_I2CM_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CM Data */
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#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) I2CM Debug Control */
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#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CS Control A */
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#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CS Control B */
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#define REG_SERCOM0_I2CS_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CS Control C */
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#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
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#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
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#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
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#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CS Status */
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#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
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#define REG_SERCOM0_I2CS_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) I2CS Length */
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#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CS Address */
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#define REG_SERCOM0_I2CS_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CS Data */
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#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) SPI Control A */
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#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) SPI Control B */
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#define REG_SERCOM0_SPI_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) SPI Control C */
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#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4000300CUL) /**< \brief (SERCOM0) SPI Baud Rate */
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#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
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#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
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#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
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#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) SPI Status */
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#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
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#define REG_SERCOM0_SPI_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) SPI Length */
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#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) SPI Address */
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#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) SPI Data */
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#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) SPI Debug Control */
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#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) USART Control A */
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#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) USART Control B */
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#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) USART Control C */
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#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4000300CUL) /**< \brief (SERCOM0) USART Baud Rate */
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#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4000300EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
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#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
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#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
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#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
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#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) USART Status */
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#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
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#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL) /**< \brief (SERCOM0) USART Receive Error Count */
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#define REG_SERCOM0_USART_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) USART Length */
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#define REG_SERCOM0_USART_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) USART Data */
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#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) USART Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for SERCOM0 peripheral ========== */
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#define SERCOM0_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
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#define SERCOM0_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
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#define SERCOM0_DMA 1 // DMA support implemented?
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#define SERCOM0_DMAC_ID_RX 4 // Index of DMA RX trigger
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#define SERCOM0_DMAC_ID_TX 5 // Index of DMA TX trigger
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#define SERCOM0_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
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#define SERCOM0_GCLK_ID_CORE 7
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#define SERCOM0_GCLK_ID_SLOW 3
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#define SERCOM0_INT_MSB 6
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#define SERCOM0_PMSB 3
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#define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
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#define SERCOM0_SE_CNT 1 // SE counter included?
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#define SERCOM0_SPI 1 // SPI mode implemented?
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#define SERCOM0_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
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#define SERCOM0_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
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#define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
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#define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
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#define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
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#define SERCOM0_TWIM 1 // TWI Master mode implemented?
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#define SERCOM0_TWIS 1 // TWI Slave mode implemented?
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#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
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#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
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#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
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#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
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#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
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#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented?
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#define SERCOM0_TWI_HSMODE 1 // USART mode implemented?
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#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
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#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
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#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
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#define SERCOM0_USART 1 // USART mode implemented?
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#define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
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#define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
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#define SERCOM0_USART_FLOW_CTRL 1 // USART flow control implemented?
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#define SERCOM0_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
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#define SERCOM0_USART_IRDA 1 // USART IrDA implemented?
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#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented?
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#define SERCOM0_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
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#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented?
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#define SERCOM0_USART_SAMPA_EXT 1 // USART sample adjust implemented?
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#define SERCOM0_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
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#endif /* _SAMD51_SERCOM0_INSTANCE_ */
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