mirror of https://github.com/Desuuuu/klipper.git
85 lines
7.1 KiB
C
85 lines
7.1 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_TWI1_INSTANCE_
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#define _SAM4E_TWI1_INSTANCE_
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/* ========== Register definition for TWI1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TWI1_CR (0x400AC000U) /**< \brief (TWI1) Control Register */
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#define REG_TWI1_MMR (0x400AC004U) /**< \brief (TWI1) Master Mode Register */
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#define REG_TWI1_SMR (0x400AC008U) /**< \brief (TWI1) Slave Mode Register */
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#define REG_TWI1_IADR (0x400AC00CU) /**< \brief (TWI1) Internal Address Register */
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#define REG_TWI1_CWGR (0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */
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#define REG_TWI1_SR (0x400AC020U) /**< \brief (TWI1) Status Register */
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#define REG_TWI1_IER (0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */
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#define REG_TWI1_IDR (0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */
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#define REG_TWI1_IMR (0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */
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#define REG_TWI1_RHR (0x400AC030U) /**< \brief (TWI1) Receive Holding Register */
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#define REG_TWI1_THR (0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */
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#define REG_TWI1_WPROT_MODE (0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */
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#define REG_TWI1_WPROT_STATUS (0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */
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#define REG_TWI1_RPR (0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */
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#define REG_TWI1_RCR (0x400AC104U) /**< \brief (TWI1) Receive Counter Register */
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#define REG_TWI1_TPR (0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */
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#define REG_TWI1_TCR (0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */
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#define REG_TWI1_RNPR (0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */
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#define REG_TWI1_RNCR (0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */
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#define REG_TWI1_TNPR (0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */
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#define REG_TWI1_TNCR (0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */
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#define REG_TWI1_PTCR (0x400AC120U) /**< \brief (TWI1) Transfer Control Register */
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#define REG_TWI1_PTSR (0x400AC124U) /**< \brief (TWI1) Transfer Status Register */
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#else
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#define REG_TWI1_CR (*(WoReg*)0x400AC000U) /**< \brief (TWI1) Control Register */
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#define REG_TWI1_MMR (*(RwReg*)0x400AC004U) /**< \brief (TWI1) Master Mode Register */
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#define REG_TWI1_SMR (*(RwReg*)0x400AC008U) /**< \brief (TWI1) Slave Mode Register */
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#define REG_TWI1_IADR (*(RwReg*)0x400AC00CU) /**< \brief (TWI1) Internal Address Register */
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#define REG_TWI1_CWGR (*(RwReg*)0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */
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#define REG_TWI1_SR (*(RoReg*)0x400AC020U) /**< \brief (TWI1) Status Register */
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#define REG_TWI1_IER (*(WoReg*)0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */
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#define REG_TWI1_IDR (*(WoReg*)0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */
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#define REG_TWI1_IMR (*(RoReg*)0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */
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#define REG_TWI1_RHR (*(RoReg*)0x400AC030U) /**< \brief (TWI1) Receive Holding Register */
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#define REG_TWI1_THR (*(WoReg*)0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */
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#define REG_TWI1_WPROT_MODE (*(RwReg*)0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */
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#define REG_TWI1_WPROT_STATUS (*(RoReg*)0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */
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#define REG_TWI1_RPR (*(RwReg*)0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */
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#define REG_TWI1_RCR (*(RwReg*)0x400AC104U) /**< \brief (TWI1) Receive Counter Register */
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#define REG_TWI1_TPR (*(RwReg*)0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */
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#define REG_TWI1_TCR (*(RwReg*)0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */
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#define REG_TWI1_RNPR (*(RwReg*)0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */
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#define REG_TWI1_RNCR (*(RwReg*)0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */
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#define REG_TWI1_TNPR (*(RwReg*)0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */
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#define REG_TWI1_TNCR (*(RwReg*)0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */
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#define REG_TWI1_PTCR (*(WoReg*)0x400AC120U) /**< \brief (TWI1) Transfer Control Register */
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#define REG_TWI1_PTSR (*(RoReg*)0x400AC124U) /**< \brief (TWI1) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_TWI1_INSTANCE_ */
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