mirror of https://github.com/Desuuuu/klipper.git
95 lines
8.1 KiB
C
95 lines
8.1 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4S_SSC_INSTANCE_
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#define _SAM4S_SSC_INSTANCE_
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/* ========== Register definition for SSC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
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#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
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#define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
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#define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */
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#define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
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#define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
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#define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
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#define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
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#define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
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#define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
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#define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */
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#define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */
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#else
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#define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */
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#define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
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#define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
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#define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
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#define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
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#define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
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#define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
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#define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
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#define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
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#define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
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#define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
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#define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
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#define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */
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#define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
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#define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
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#define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
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#define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
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#define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
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#define REG_SSC_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
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#define REG_SSC_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
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#define REG_SSC_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
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#define REG_SSC_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
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#define REG_SSC_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
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#define REG_SSC_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
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#define REG_SSC_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
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#define REG_SSC_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
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#define REG_SSC_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
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#define REG_SSC_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4S_SSC_INSTANCE_ */
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