mirror of https://github.com/Desuuuu/klipper.git
1703 lines
56 KiB
C
1703 lines
56 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_can.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief CAN HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Controller Area Network (CAN) peripheral:
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* + Initialization and de-initialization functions
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* + IO operation functions
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* + Peripheral Control functions
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* + Peripheral State and Error functions
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Enable the CAN controller interface clock using
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__HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
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-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
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(#) CAN pins configuration
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(++) Enable the clock for the CAN GPIOs using the following function:
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__HAL_RCC_GPIOx_CLK_ENABLE();
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(++) Connect and configure the involved CAN pins using the
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following function HAL_GPIO_Init();
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(#) Initialize and configure the CAN using HAL_CAN_Init() function.
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(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
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(#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
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(#) Receive a CAN frame using HAL_CAN_Receive() function.
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(#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
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*** Polling mode IO operation ***
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=================================
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[..]
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(+) Start the CAN peripheral transmission and wait the end of this operation
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using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
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according to his end application
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(+) Start the CAN peripheral reception and wait the end of this operation
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using HAL_CAN_Receive(), at this stage user can specify the value of timeout
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according to his end application
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*** Interrupt mode IO operation ***
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===================================
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[..]
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(+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
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(+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
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(+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
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(+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
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add his own code by customization of function pointer HAL_CAN_TxCpltCallback
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(+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
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add his own code by customization of function pointer HAL_CAN_ErrorCallback
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*** CAN HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in CAN HAL driver.
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(+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
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(+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
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(+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
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(+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
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(+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
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[..]
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(@) You can refer to the CAN HAL driver header file for more useful macros
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup CAN CAN
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* @brief CAN driver modules
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* @{
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*/
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#ifdef HAL_CAN_MODULE_ENABLED
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#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
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defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup CAN_Private_Constants CAN Private Constants
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* @{
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*/
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#define CAN_TIMEOUT_VALUE 10U
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup CAN_Private_Functions CAN Private Functions
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* @{
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*/
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static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
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static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CAN_Exported_Functions CAN Exported Functions
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* @{
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*/
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/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### Initialization and de-initialization functions #####
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==============================================================================
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[..] This section provides functions allowing to:
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(+) Initialize and configure the CAN.
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(+) De-initialize the CAN.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the CAN peripheral according to the specified
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* parameters in the CAN_InitStruct.
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
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{
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uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
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uint32_t tickstart = 0U;
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uint32_t tmp_mcr = 0U;
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/* Check CAN handle */
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if(hcan == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
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assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
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assert_param(IS_CAN_MODE(hcan->Init.Mode));
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assert_param(IS_CAN_SJW(hcan->Init.SJW));
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assert_param(IS_CAN_BS1(hcan->Init.BS1));
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assert_param(IS_CAN_BS2(hcan->Init.BS2));
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assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
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if(hcan->State == HAL_CAN_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hcan->Lock = HAL_UNLOCKED;
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/* Init the low level hardware */
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HAL_CAN_MspInit(hcan);
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}
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/* Initialize the CAN state*/
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hcan->State = HAL_CAN_STATE_BUSY;
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/* Exit from sleep mode */
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CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
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/* Request initialisation */
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SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Wait the acknowledge */
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while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
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{
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if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
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{
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hcan->State= HAL_CAN_STATE_TIMEOUT;
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/* Process unlocked */
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__HAL_UNLOCK(hcan);
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return HAL_TIMEOUT;
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}
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}
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/* Check acknowledge */
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if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
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{
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/* Set the time triggered communication mode */
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if (hcan->Init.TTCM == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_TTCM);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
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}
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/* Set the automatic bus-off management */
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if (hcan->Init.ABOM == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_ABOM);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
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}
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/* Set the automatic wake-up mode */
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if (hcan->Init.AWUM == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_AWUM);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
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}
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/* Set the no automatic retransmission */
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if (hcan->Init.NART == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_NART);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
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}
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/* Set the receive FIFO locked mode */
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if (hcan->Init.RFLM == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_RFLM);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
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}
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/* Set the transmit FIFO priority */
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if (hcan->Init.TXFP == ENABLE)
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{
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SET_BIT(tmp_mcr, CAN_MCR_TXFP);
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}
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else
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{
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CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
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}
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/* Update register MCR */
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MODIFY_REG(hcan->Instance->MCR,
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CAN_MCR_TTCM |
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CAN_MCR_ABOM |
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CAN_MCR_AWUM |
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CAN_MCR_NART |
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CAN_MCR_RFLM |
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CAN_MCR_TXFP,
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tmp_mcr);
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/* Set the bit timing register */
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WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
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hcan->Init.SJW |
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hcan->Init.BS1 |
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hcan->Init.BS2 |
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(hcan->Init.Prescaler - 1U)));
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/* Request leave initialisation */
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CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Wait the acknowledge */
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while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
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{
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if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
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{
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hcan->State= HAL_CAN_STATE_TIMEOUT;
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/* Process unlocked */
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__HAL_UNLOCK(hcan);
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return HAL_TIMEOUT;
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}
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}
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/* Check acknowledged */
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if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
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{
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status = CAN_INITSTATUS_SUCCESS;
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}
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}
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if(status == CAN_INITSTATUS_SUCCESS)
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{
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/* Set CAN error code to none */
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hcan->ErrorCode = HAL_CAN_ERROR_NONE;
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/* Initialize the CAN state */
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hcan->State = HAL_CAN_STATE_READY;
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/* Return function status */
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return HAL_OK;
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}
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else
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{
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/* Initialize the CAN state */
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hcan->State = HAL_CAN_STATE_ERROR;
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/* Return function status */
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return HAL_ERROR;
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}
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}
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/**
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* @brief Configures the CAN reception filter according to the specified
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* parameters in the CAN_FilterInitStruct.
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
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* contains the filter configuration information.
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* @retval None
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*/
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HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
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{
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uint32_t filternbrbitpos = 0U;
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hcan);
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/* Check the parameters */
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assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
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assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
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assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
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assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
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assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
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assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
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filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
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/* Initialisation mode for the filter */
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/* Select the start slave bank */
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MODIFY_REG(hcan->Instance->FMR ,
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CAN_FMR_CAN2SB ,
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CAN_FMR_FINIT |
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(uint32_t)(sFilterConfig->BankNumber << 8U) );
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/* Filter Deactivation */
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CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
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/* Filter Scale */
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if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
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{
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/* 16-bit scale for the filter */
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CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
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/* First 16-bit identifier and First 16-bit mask */
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/* Or First 16-bit identifier and Second 16-bit identifier */
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hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
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((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
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(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
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/* Second 16-bit identifier and Second 16-bit mask */
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/* Or Third 16-bit identifier and Fourth 16-bit identifier */
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hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
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((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
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(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
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}
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if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
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{
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/* 32-bit scale for the filter */
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SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
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/* 32-bit identifier or First 32-bit identifier */
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hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
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((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
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(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
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/* 32-bit mask or Second 32-bit identifier */
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hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
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((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
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(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
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}
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/* Filter Mode */
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if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
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{
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/*Id/Mask mode for the filter*/
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CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
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}
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else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
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{
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/*Identifier list mode for the filter*/
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SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
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}
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/* Filter FIFO assignment */
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if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
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{
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/* FIFO 0 assignation for the filter */
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CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
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}
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else
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{
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/* FIFO 1 assignation for the filter */
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SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
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}
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/* Filter activation */
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if (sFilterConfig->FilterActivation == ENABLE)
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{
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SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
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}
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/* Leave the initialisation mode for the filter */
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CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Deinitializes the CANx peripheral registers to their default reset values.
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
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{
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/* Check CAN handle */
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if(hcan == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
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/* Change CAN state */
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hcan->State = HAL_CAN_STATE_BUSY;
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/* DeInit the low level hardware */
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HAL_CAN_MspDeInit(hcan);
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/* Change CAN state */
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hcan->State = HAL_CAN_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hcan);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Initializes the CAN MSP.
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval None
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*/
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__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hcan);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_CAN_MspInit can be implemented in the user file
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*/
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}
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/**
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* @brief DeInitializes the CAN MSP.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hcan);
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_MspDeInit can be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
|
|
* @brief I/O operation functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### IO operation functions #####
|
|
==============================================================================
|
|
[..] This section provides functions allowing to:
|
|
(+) Transmit a CAN frame message.
|
|
(+) Receive a CAN frame message.
|
|
(+) Enter CAN peripheral in sleep mode.
|
|
(+) Wake up the CAN peripheral from sleep mode.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Initiates and transmits a CAN frame message.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @param Timeout: Specify Timeout value
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
|
|
{
|
|
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
|
|
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
|
|
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
|
|
|
|
if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
|
|
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
|
|
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
|
|
{
|
|
/* Process locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Change CAN state */
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
break;
|
|
}
|
|
|
|
/* Select one empty transmit mailbox */
|
|
if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_0;
|
|
}
|
|
else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_1;
|
|
}
|
|
else
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_2;
|
|
}
|
|
|
|
/* Set up the Id */
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
|
|
if (hcan->pTxMsg->IDE == CAN_ID_STD)
|
|
{
|
|
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
|
|
hcan->pTxMsg->RTR);
|
|
}
|
|
else
|
|
{
|
|
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
|
|
hcan->pTxMsg->IDE |
|
|
hcan->pTxMsg->RTR);
|
|
}
|
|
|
|
/* Set up the DLC */
|
|
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
|
|
|
|
/* Set up the data field */
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
|
|
/* Request transmission */
|
|
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Check End of transmission flag */
|
|
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
|
|
{
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|
{
|
|
hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
|
|
/* Cancel transmission */
|
|
__HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
/* Change CAN state */
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_BUSY_TX */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
break;
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_ERROR;
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Initiates and transmits a CAN frame message.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
|
|
{
|
|
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
|
|
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
|
|
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
|
|
|
|
if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
|
|
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
|
|
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Select one empty transmit mailbox */
|
|
if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_0;
|
|
}
|
|
else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_1;
|
|
}
|
|
else
|
|
{
|
|
transmitmailbox = CAN_TXMAILBOX_2;
|
|
}
|
|
|
|
/* Set up the Id */
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
|
|
if(hcan->pTxMsg->IDE == CAN_ID_STD)
|
|
{
|
|
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
|
|
hcan->pTxMsg->RTR);
|
|
}
|
|
else
|
|
{
|
|
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
|
|
hcan->pTxMsg->IDE |
|
|
hcan->pTxMsg->RTR);
|
|
}
|
|
|
|
/* Set up the DLC */
|
|
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
|
|
|
|
/* Set up the data field */
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
|
|
((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
|
|
|
|
/* Change CAN state */
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
break;
|
|
}
|
|
|
|
/* Set CAN error code to none */
|
|
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Request transmission */
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
|
|
|
|
/* Enable interrupts: */
|
|
/* - Enable Error warning Interrupt */
|
|
/* - Enable Error passive Interrupt */
|
|
/* - Enable Bus-off Interrupt */
|
|
/* - Enable Last error code Interrupt */
|
|
/* - Enable Error Interrupt */
|
|
/* - Enable Transmit mailbox empty Interrupt */
|
|
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
|
|
CAN_IT_EPV |
|
|
CAN_IT_BOF |
|
|
CAN_IT_LEC |
|
|
CAN_IT_ERR |
|
|
CAN_IT_TME );
|
|
}
|
|
else
|
|
{
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_ERROR;
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Receives a correct CAN frame.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @param FIFONumber: FIFO Number value
|
|
* @param Timeout: Specify Timeout value
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
CanRxMsgTypeDef* pRxMsg = NULL;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CAN_FIFO(FIFONumber));
|
|
|
|
/* Check if CAN state is not busy for RX FIFO0 */
|
|
if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Check if CAN state is not busy for RX FIFO1 */
|
|
if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Change CAN state */
|
|
if (FIFONumber == CAN_FIFO0)
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
break;
|
|
}
|
|
}
|
|
else /* FIFONumber == CAN_FIFO1 */
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
break;
|
|
}
|
|
}
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Check pending message */
|
|
while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
|
|
{
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|
{
|
|
hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set RxMsg pointer */
|
|
if(FIFONumber == CAN_FIFO0)
|
|
{
|
|
pRxMsg = hcan->pRxMsg;
|
|
}
|
|
else /* FIFONumber == CAN_FIFO1 */
|
|
{
|
|
pRxMsg = hcan->pRx1Msg;
|
|
}
|
|
|
|
/* Get the Id */
|
|
pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
|
|
if (pRxMsg->IDE == CAN_ID_STD)
|
|
{
|
|
pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
|
|
}
|
|
else
|
|
{
|
|
pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
|
|
}
|
|
|
|
pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
|
|
/* Get the DLC */
|
|
pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
|
|
/* Get the FMI */
|
|
pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
|
|
/* Get the FIFONumber */
|
|
pRxMsg->FIFONumber = FIFONumber;
|
|
/* Get the data field */
|
|
pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
|
|
pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
|
|
pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
|
|
pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
|
|
pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
|
|
pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
|
|
pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
|
|
pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
|
|
|
|
/* Release the FIFO */
|
|
if(FIFONumber == CAN_FIFO0)
|
|
{
|
|
/* Release FIFO0 */
|
|
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
|
|
}
|
|
else /* FIFONumber == CAN_FIFO1 */
|
|
{
|
|
/* Release FIFO1 */
|
|
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
|
|
}
|
|
|
|
/* Change CAN state */
|
|
if (FIFONumber == CAN_FIFO0)
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_BUSY_RX0 */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
break;
|
|
}
|
|
}
|
|
else /* FIFONumber == CAN_FIFO1 */
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
break;
|
|
default: /* HAL_CAN_STATE_BUSY_RX1 */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Receives a correct CAN frame.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @param FIFONumber: Specify the FIFO number
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_CAN_FIFO(FIFONumber));
|
|
|
|
/* Check if CAN state is not busy for RX FIFO0 */
|
|
if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Check if CAN state is not busy for RX FIFO1 */
|
|
if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Change CAN state */
|
|
if(FIFONumber == CAN_FIFO0)
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
break;
|
|
}
|
|
}
|
|
else /* FIFONumber == CAN_FIFO1 */
|
|
{
|
|
switch(hcan->State)
|
|
{
|
|
case(HAL_CAN_STATE_BUSY_TX):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
break;
|
|
case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
break;
|
|
default: /* HAL_CAN_STATE_READY */
|
|
hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
break;
|
|
}
|
|
}
|
|
/* Set CAN error code to none */
|
|
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
|
|
|
|
/* Enable interrupts: */
|
|
/* - Enable Error warning Interrupt */
|
|
/* - Enable Error passive Interrupt */
|
|
/* - Enable Bus-off Interrupt */
|
|
/* - Enable Last error code Interrupt */
|
|
/* - Enable Error Interrupt */
|
|
/* - Enable Transmit mailbox empty Interrupt */
|
|
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
|
|
CAN_IT_EPV |
|
|
CAN_IT_BOF |
|
|
CAN_IT_LEC |
|
|
CAN_IT_ERR |
|
|
CAN_IT_TME );
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
if(FIFONumber == CAN_FIFO0)
|
|
{
|
|
/* Enable FIFO 0 overrun and message pending Interrupt */
|
|
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
|
|
}
|
|
else
|
|
{
|
|
/* Enable FIFO 1 overrun and message pending Interrupt */
|
|
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Enters the Sleep (low power) mode.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_BUSY;
|
|
|
|
/* Request Sleep mode */
|
|
MODIFY_REG(hcan->Instance->MCR,
|
|
CAN_MCR_INRQ ,
|
|
CAN_MCR_SLEEP );
|
|
|
|
/* Sleep mode status */
|
|
if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
|
|
HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait the acknowledge */
|
|
while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
|
|
HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
|
|
{
|
|
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
|
|
{
|
|
hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
|
|
* is in the normal mode.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hcan);
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_BUSY;
|
|
|
|
/* Wake up request */
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Sleep mode status */
|
|
while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
|
|
{
|
|
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
|
|
{
|
|
hcan->State= HAL_CAN_STATE_TIMEOUT;
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hcan);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Handles CAN interrupt request
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
|
|
{
|
|
uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
|
|
uint32_t errorcode = HAL_CAN_ERROR_NONE;
|
|
|
|
/* Check Overrun flag for FIFO0 */
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
|
|
if((tmp1 != 0U) && tmp2)
|
|
{
|
|
/* Set CAN error code to FOV0 error */
|
|
errorcode |= HAL_CAN_ERROR_FOV0;
|
|
|
|
/* Clear FIFO0 Overrun Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
|
|
}
|
|
|
|
/* Check Overrun flag for FIFO1 */
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
|
|
if((tmp1 != 0U) && tmp2)
|
|
{
|
|
/* Set CAN error code to FOV1 error */
|
|
errorcode |= HAL_CAN_ERROR_FOV1;
|
|
|
|
/* Clear FIFO1 Overrun Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
|
|
}
|
|
|
|
/* Check End of transmission flag */
|
|
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
|
|
{
|
|
/* Check Transmit request completion status */
|
|
tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
|
|
tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
|
|
tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
|
|
if(tmp1 || tmp2 || tmp3)
|
|
{
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
|
|
tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
|
|
tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
|
|
/* Check Transmit success */
|
|
if((tmp1) || (tmp2) || (tmp3))
|
|
{
|
|
/* Call transmit function */
|
|
CAN_Transmit_IT(hcan);
|
|
}
|
|
else /* Transmit failure */
|
|
{
|
|
/* Set CAN error code to TXFAIL error */
|
|
errorcode |= HAL_CAN_ERROR_TXFAIL;
|
|
}
|
|
|
|
/* Clear transmission status flags (RQCPx and TXOKx) */
|
|
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
|
|
CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
|
|
}
|
|
}
|
|
|
|
tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
|
|
/* Check End of reception flag for FIFO0 */
|
|
if((tmp1 != 0U) && tmp2)
|
|
{
|
|
/* Call receive function */
|
|
CAN_Receive_IT(hcan, CAN_FIFO0);
|
|
}
|
|
|
|
tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
|
|
/* Check End of reception flag for FIFO1 */
|
|
if((tmp1 != 0U) && tmp2)
|
|
{
|
|
/* Call receive function */
|
|
CAN_Receive_IT(hcan, CAN_FIFO1);
|
|
}
|
|
|
|
/* Set error code in handle */
|
|
hcan->ErrorCode |= errorcode;
|
|
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
|
|
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
|
|
/* Check Error Warning Flag */
|
|
if(tmp1 && tmp2 && tmp3)
|
|
{
|
|
/* Set CAN error code to EWG error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
|
|
/* No need for clear of Error Warning Flag as read-only */
|
|
}
|
|
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
|
|
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
|
|
/* Check Error Passive Flag */
|
|
if(tmp1 && tmp2 && tmp3)
|
|
{
|
|
/* Set CAN error code to EPV error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
|
|
/* No need for clear of Error Passive Flag as read-only */
|
|
}
|
|
|
|
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
|
|
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
|
|
/* Check Bus-Off Flag */
|
|
if(tmp1 && tmp2 && tmp3)
|
|
{
|
|
/* Set CAN error code to BOF error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
|
|
/* No need for clear of Bus-Off Flag as read-only */
|
|
}
|
|
|
|
tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
|
|
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
|
|
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
|
|
/* Check Last error code Flag */
|
|
if((!tmp1) && tmp2 && tmp3)
|
|
{
|
|
tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
|
|
switch(tmp1)
|
|
{
|
|
case(CAN_ESR_LEC_0):
|
|
/* Set CAN error code to STF error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_STF;
|
|
break;
|
|
case(CAN_ESR_LEC_1):
|
|
/* Set CAN error code to FOR error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
|
|
break;
|
|
case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
|
|
/* Set CAN error code to ACK error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
|
|
break;
|
|
case(CAN_ESR_LEC_2):
|
|
/* Set CAN error code to BR error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_BR;
|
|
break;
|
|
case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
|
|
/* Set CAN error code to BD error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_BD;
|
|
break;
|
|
case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
|
|
/* Set CAN error code to CRC error */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Clear Last error code Flag */
|
|
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
|
|
}
|
|
|
|
/* Call the Error call Back in case of Errors */
|
|
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
|
|
{
|
|
/* Clear ERRI Flag */
|
|
hcan->Instance->MSR = CAN_MSR_ERRI;
|
|
/* Set the CAN state ready to be able to start again the process */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
|
|
/* Disable interrupts: */
|
|
/* - Disable Error warning Interrupt */
|
|
/* - Disable Error passive Interrupt */
|
|
/* - Disable Bus-off Interrupt */
|
|
/* - Disable Last error code Interrupt */
|
|
/* - Disable Error Interrupt */
|
|
/* - Disable FIFO 0 message pending Interrupt */
|
|
/* - Disable FIFO 0 Overrun Interrupt */
|
|
/* - Disable FIFO 1 message pending Interrupt */
|
|
/* - Disable FIFO 1 Overrun Interrupt */
|
|
/* - Disable Transmit mailbox empty Interrupt */
|
|
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
|
|
CAN_IT_EPV |
|
|
CAN_IT_BOF |
|
|
CAN_IT_LEC |
|
|
CAN_IT_ERR |
|
|
CAN_IT_FMP0|
|
|
CAN_IT_FOV0|
|
|
CAN_IT_FMP1|
|
|
CAN_IT_FOV1|
|
|
CAN_IT_TME );
|
|
|
|
/* Call Error callback function */
|
|
HAL_CAN_ErrorCallback(hcan);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Transmission complete callback in non blocking mode
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hcan);
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxCpltCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Transmission complete callback in non blocking mode
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hcan);
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_RxCpltCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Error CAN callback.
|
|
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hcan);
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_ErrorCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
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* @brief CAN Peripheral State functions
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*
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@verbatim
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==============================================================================
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##### Peripheral State and Error functions #####
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==============================================================================
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[..]
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This subsection provides functions allowing to :
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(+) Check the CAN state.
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(+) Check CAN Errors detected during interrupt process
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@endverbatim
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* @{
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*/
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/**
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* @brief return the CAN state
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval HAL state
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*/
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HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
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{
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/* Return CAN state */
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return hcan->State;
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}
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/**
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* @brief Return the CAN error code
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval CAN Error Code
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*/
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uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
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{
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return hcan->ErrorCode;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup CAN_Private_Functions
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* @{
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*/
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/**
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* @brief Initiates and transmits a CAN frame message.
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* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @retval HAL status
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*/
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static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
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{
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/* Disable Transmit mailbox empty Interrupt */
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__HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
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if(hcan->State == HAL_CAN_STATE_BUSY_TX)
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{
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/* Disable interrupts: */
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/* - Disable Error warning Interrupt */
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/* - Disable Error passive Interrupt */
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/* - Disable Bus-off Interrupt */
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/* - Disable Last error code Interrupt */
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/* - Disable Error Interrupt */
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__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
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CAN_IT_EPV |
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CAN_IT_BOF |
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CAN_IT_LEC |
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CAN_IT_ERR);
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}
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/* Change CAN state */
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switch(hcan->State)
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{
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case(HAL_CAN_STATE_BUSY_TX_RX0):
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hcan->State = HAL_CAN_STATE_BUSY_RX0;
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break;
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case(HAL_CAN_STATE_BUSY_TX_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_RX1;
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break;
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case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
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break;
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default: /* HAL_CAN_STATE_BUSY_TX */
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hcan->State = HAL_CAN_STATE_READY;
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break;
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}
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/* Transmission complete callback */
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HAL_CAN_TxCpltCallback(hcan);
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return HAL_OK;
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}
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/**
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* @brief Receives a correct CAN frame.
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* @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
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* the configuration information for the specified CAN.
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* @param FIFONumber: Specify the FIFO number
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* @retval HAL status
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* @retval None
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*/
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static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
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{
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uint32_t tmp1 = 0U;
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CanRxMsgTypeDef* pRxMsg = NULL;
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/* Set RxMsg pointer */
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if(FIFONumber == CAN_FIFO0)
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{
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pRxMsg = hcan->pRxMsg;
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}
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else /* FIFONumber == CAN_FIFO1 */
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{
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pRxMsg = hcan->pRx1Msg;
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}
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/* Get the Id */
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pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
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if (pRxMsg->IDE == CAN_ID_STD)
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{
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pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
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}
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else
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{
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pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
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}
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pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
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/* Get the DLC */
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pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
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/* Get the FIFONumber */
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pRxMsg->FIFONumber = FIFONumber;
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/* Get the FMI */
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pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
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/* Get the data field */
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pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
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pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
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pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
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pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
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pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
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pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
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pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
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pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
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/* Release the FIFO */
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/* Release FIFO0 */
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if (FIFONumber == CAN_FIFO0)
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{
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__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
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/* Disable FIFO 0 overrun and message pending Interrupt */
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__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
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}
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/* Release FIFO1 */
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else /* FIFONumber == CAN_FIFO1 */
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{
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__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
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/* Disable FIFO 1 overrun and message pending Interrupt */
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__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
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}
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tmp1 = hcan->State;
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if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
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{
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/* Disable interrupts: */
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/* - Disable Error warning Interrupt */
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/* - Disable Error passive Interrupt */
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/* - Disable Bus-off Interrupt */
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/* - Disable Last error code Interrupt */
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/* - Disable Error Interrupt */
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__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
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CAN_IT_EPV |
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CAN_IT_BOF |
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CAN_IT_LEC |
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CAN_IT_ERR);
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}
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/* Change CAN state */
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if (FIFONumber == CAN_FIFO0)
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{
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switch(hcan->State)
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{
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case(HAL_CAN_STATE_BUSY_TX_RX0):
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hcan->State = HAL_CAN_STATE_BUSY_TX;
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break;
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case(HAL_CAN_STATE_BUSY_RX0_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_RX1;
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break;
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case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
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break;
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default: /* HAL_CAN_STATE_BUSY_RX0 */
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hcan->State = HAL_CAN_STATE_READY;
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break;
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}
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}
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else /* FIFONumber == CAN_FIFO1 */
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{
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switch(hcan->State)
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{
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case(HAL_CAN_STATE_BUSY_TX_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_TX;
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break;
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case(HAL_CAN_STATE_BUSY_RX0_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_RX0;
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break;
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case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
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hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
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break;
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default: /* HAL_CAN_STATE_BUSY_RX1 */
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hcan->State = HAL_CAN_STATE_READY;
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break;
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}
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}
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/* Receive complete callback */
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HAL_CAN_RxCpltCallback(hcan);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @}
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*/
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#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
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#endif /* HAL_CAN_MODULE_ENABLED */
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/**
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* @}
|
|
*/
|
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|
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/**
|
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* @}
|
|
*/
|
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|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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