mirror of https://github.com/Desuuuu/klipper.git
250 lines
6.3 KiB
C
250 lines
6.3 KiB
C
/*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PRU_CFG_H_
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#define _PRU_CFG_H_
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/* PRU_CFG register set */
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typedef struct {
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/* PRU_CFG_REVID register bit field */
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union {
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volatile uint32_t REVID;
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volatile struct {
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unsigned REVID : 32;
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} REVID_bit;
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}; // 0x0
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/* PRU_CFG_SYSCFG register bit field */
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union {
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volatile uint32_t SYSCFG;
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volatile struct {
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unsigned IDLE_MODE : 2;
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unsigned STANDBY_MODE : 2;
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unsigned STANDBY_INIT : 1;
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unsigned SUB_MWAIT : 1;
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unsigned rsvd6 : 26;
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} SYSCFG_bit;
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}; // 0x4
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/* PRU_CFG_GPCFG0 register bit field */
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union {
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volatile uint32_t GPCFG0;
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volatile struct {
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unsigned PRU0_GPI_MODE : 2; // 1:0
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unsigned PRU0_GPI_CLK_MODE : 1; // 2
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unsigned PRU0_GPI_DIV0 : 5; // 7:3
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unsigned PRU0_GPI_DIV1 : 5; // 12:8
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unsigned PRU0_GPI_SB : 1; // 13
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unsigned PRU0_GPO_MODE : 1; // 14
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unsigned PRU0_GPO_DIV0 : 5; // 19:15
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unsigned PRU0_GPO_DIV1 : 5; // 24:20
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unsigned PRU0_GPO_SH_SEL : 1; // 25
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unsigned rsvd26 : 6; // 31:26
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} GPCFG0_bit;
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}; // 0x8
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/* PRU_CFG_GPCFG1 register bit field */
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union {
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volatile uint32_t GPCFG1;
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volatile struct {
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unsigned PRU1_GPI_MODE : 2; // 1:0
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unsigned PRU1_GPI_CLK_MODE : 1; // 2
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unsigned PRU1_GPI_DIV0 : 5; // 7:3
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unsigned PRU1_GPI_DIV1 : 5; // 12:8
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unsigned PRU1_GPI_SB : 1; // 13
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unsigned PRU1_GPO_MODE : 1; // 14
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unsigned PRU1_GPO_DIV0 : 5; // 19:15
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unsigned PRU1_GPO_DIV1 : 5; // 24:20
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unsigned PRU1_GPO_SH_SEL : 1; // 25
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unsigned rsvd26 : 6; // 31:26
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} GPCFG1_bit;
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}; // 0xC
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/* PRU_CFG_CGR register bit field */
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union {
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volatile uint32_t CGR;
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volatile struct {
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unsigned PRU0_CLK_STOP_REQ : 1; // 0
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unsigned PRU0_CLK_STOP_ACK : 1; // 1
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unsigned PRU0_CLK_EN : 1; // 2
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unsigned PRU1_CLK_STOP_REQ : 1; // 3
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unsigned PRU1_CLK_STOP_ACK : 1; // 4
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unsigned PRU1_CLK_EN : 1; // 5
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unsigned INTC_CLK_STOP_REQ : 1; // 6
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unsigned INTC_CLK_STOP_ACK : 1; // 7
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unsigned INTC_CLK_EN : 1; // 8
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unsigned UART_CLK_STOP_REQ : 1; // 9
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unsigned UART_CLK_STOP_ACK : 1; // 10
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unsigned UART_CLK_EN : 1; // 11
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unsigned ECAP_CLK_STOP_REQ : 1; // 12
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unsigned ECAP_CLK_STOP_ACK : 1; // 13
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unsigned ECAP_CLK_EN : 1; // 14
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unsigned IEP_CLK_STOP_REQ : 1; // 15
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unsigned IEP_CLK_STOP_ACK : 1; // 16
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unsigned IEP_CLK_EN : 1; // 17
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unsigned rsvd18 : 14; // 31:18
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} CGR_bit;
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}; // 0x10
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/* PRU_CFG_ISRP register bit field */
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union {
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volatile uint32_t ISRP;
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volatile struct {
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unsigned PRU0_IMEM_PE_RAW : 4; // 3:0
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unsigned PRU0_DMEM_PE_RAW : 4; // 7:4
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unsigned PRU1_IMEM_PE_RAW : 4; // 11:8
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unsigned PRU1_DMEM_PE_RAW : 4; // 15:12
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unsigned RAM_PE_RAW : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} ISRP_bit;
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}; // 0x14
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/* PRU_CFG_ISP register bit field */
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union {
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volatile uint32_t ISP;
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volatile struct {
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unsigned PRU0_IMEM_PE : 4; // 3:0
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unsigned PRU0_DMEM_PE : 4; // 7:4
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unsigned PRU1_IMEM_PE : 4; // 11:8
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unsigned PRU1_DMEM_PE : 4; // 15:12
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unsigned RAM_PE : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} ISP_bit;
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}; // 0x18
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/* PRU_CFG_IESP register bit field */
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union {
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volatile uint32_t IESP;
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volatile struct {
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unsigned PRU0_IMEM_PE_SET : 4; // 3:0
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unsigned PRU0_DMEM_PE_SET : 4; // 7:4
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unsigned PRU1_IMEM_PE_SET : 4; // 11:8
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unsigned PRU1_DMEM_PE_SET : 4; // 15:12
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unsigned RAM_PE_SET : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} IESP_bit;
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}; // 0x1C
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/* PRU_CFG_IECP register bit field */
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union {
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volatile uint32_t IECP;
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volatile struct {
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unsigned PRU0_IMEM_PE_CLR : 4; // 3:0
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unsigned PRU0_DMEM_PE_CLR : 4; // 7:4
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unsigned PRU1_IMEM_PE_CLR : 4; // 11:8
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unsigned PRU1_DMEM_PE_CLR : 4; // 15:12
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unsigned rsvd16 : 16; // 31:16
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} IECP_bit;
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}; // 0x20
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uint32_t rsvd24; // 0x24
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/* PRU_CFG_PMAO register bit field */
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union {
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volatile uint32_t PMAO;
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volatile struct {
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unsigned PMAO_PRU0 : 1; // 0
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unsigned PMAO_PRU1 : 1; // 1
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unsigned rsvd2 : 30; // 31:2
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} PMAO_bit;
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}; // 0x28
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uint32_t rsvd2c[1]; // 0x2C
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/* PRU_CFG_IEPCLK register bit field */
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union {
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volatile uint32_t IEPCLK;
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volatile struct {
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unsigned OCP_EN : 1; // 0
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unsigned rsvd1 : 31; // 31:1
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} IEPCLK_bit;
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}; // 0x30
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/* PRU_CFG_SPP register bit field */
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union {
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volatile uint32_t SPP;
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volatile struct {
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unsigned PRU1_PAD_HP_EN : 1; // 0
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unsigned XFR_SHIFT_EN : 1; // 1
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unsigned rsvd2 : 30; // 31:2
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} SPP_bit;
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}; // 0x34
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uint32_t rsvd38[2]; // 0x38 - 0x3C
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union {
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volatile uint32_t PIN_MX;
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volatile struct {
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unsigned PIN_MUX_SEL : 8; // 7:0
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unsigned rsvd2 : 24; // 31:8
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} PIN_MX_bit;
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}; //0x40
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} pruCfg;
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#ifdef __GNUC__
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static volatile pruCfg *__CT_CFG = (void *)0x00026000;
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#define CT_CFG (*__CT_CFG)
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#else
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volatile __far pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
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#endif
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#endif /* _PRU_CFG_H_ */
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