mirror of https://github.com/Desuuuu/klipper.git
313 lines
14 KiB
C
313 lines
14 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : ROSC
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// Version : 1
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// Bus type : apb
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// Description : None
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// =============================================================================
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#ifndef HARDWARE_REGS_ROSC_DEFINED
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#define HARDWARE_REGS_ROSC_DEFINED
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// =============================================================================
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// Register : ROSC_CTRL
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// Description : Ring Oscillator control
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#define ROSC_CTRL_OFFSET _u(0x00000000)
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#define ROSC_CTRL_BITS _u(0x00ffffff)
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#define ROSC_CTRL_RESET _u(0x00000aa0)
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// -----------------------------------------------------------------------------
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// Field : ROSC_CTRL_ENABLE
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// Description : On power-up this field is initialised to ENABLE
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// The system clock must be switched to another source before
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// setting this field to DISABLE otherwise the chip will lock up
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// The 12-bit code is intended to give some protection against
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// accidental writes. An invalid setting will enable the
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// oscillator.
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// 0xd1e -> DISABLE
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// 0xfab -> ENABLE
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#define ROSC_CTRL_ENABLE_RESET "-"
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#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
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#define ROSC_CTRL_ENABLE_MSB _u(23)
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#define ROSC_CTRL_ENABLE_LSB _u(12)
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#define ROSC_CTRL_ENABLE_ACCESS "RW"
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#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
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#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
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// -----------------------------------------------------------------------------
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// Field : ROSC_CTRL_FREQ_RANGE
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// Description : Controls the number of delay stages in the ROSC ring
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// LOW uses stages 0 to 7
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// MEDIUM uses stages 0 to 5
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// HIGH uses stages 0 to 3
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// TOOHIGH uses stages 0 to 1 and should not be used because its
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// frequency exceeds design specifications
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// The clock output will not glitch when changing the range up one
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// step at a time
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// The clock output will glitch when changing the range down
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// Note: the values here are gray coded which is why HIGH comes
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// before TOOHIGH
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// 0xfa4 -> LOW
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// 0xfa5 -> MEDIUM
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// 0xfa7 -> HIGH
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// 0xfa6 -> TOOHIGH
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#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
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#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
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#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
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#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
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#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
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#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
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#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
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#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
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#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
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// =============================================================================
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// Register : ROSC_FREQA
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// Description : The FREQA & FREQB registers control the frequency by
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// controlling the drive strength of each stage
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// The drive strength has 4 levels determined by the number of
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// bits set
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// Increasing the number of bits set increases the drive strength
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// and increases the oscillation frequency
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// 0 bits set is the default drive strength
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// 1 bit set doubles the drive strength
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// 2 bits set triples drive strength
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// 3 bits set quadruples drive strength
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#define ROSC_FREQA_OFFSET _u(0x00000004)
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#define ROSC_FREQA_BITS _u(0xffff7777)
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#define ROSC_FREQA_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQA_PASSWD
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// Description : Set to 0x9696 to apply the settings
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// Any other value in this field will set all drive strengths to 0
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// 0x9696 -> PASS
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#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
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#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
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#define ROSC_FREQA_PASSWD_MSB _u(31)
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#define ROSC_FREQA_PASSWD_LSB _u(16)
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#define ROSC_FREQA_PASSWD_ACCESS "RW"
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#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQA_DS3
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// Description : Stage 3 drive strength
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#define ROSC_FREQA_DS3_RESET _u(0x0)
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#define ROSC_FREQA_DS3_BITS _u(0x00007000)
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#define ROSC_FREQA_DS3_MSB _u(14)
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#define ROSC_FREQA_DS3_LSB _u(12)
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#define ROSC_FREQA_DS3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQA_DS2
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// Description : Stage 2 drive strength
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#define ROSC_FREQA_DS2_RESET _u(0x0)
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#define ROSC_FREQA_DS2_BITS _u(0x00000700)
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#define ROSC_FREQA_DS2_MSB _u(10)
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#define ROSC_FREQA_DS2_LSB _u(8)
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#define ROSC_FREQA_DS2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQA_DS1
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// Description : Stage 1 drive strength
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#define ROSC_FREQA_DS1_RESET _u(0x0)
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#define ROSC_FREQA_DS1_BITS _u(0x00000070)
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#define ROSC_FREQA_DS1_MSB _u(6)
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#define ROSC_FREQA_DS1_LSB _u(4)
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#define ROSC_FREQA_DS1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQA_DS0
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// Description : Stage 0 drive strength
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#define ROSC_FREQA_DS0_RESET _u(0x0)
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#define ROSC_FREQA_DS0_BITS _u(0x00000007)
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#define ROSC_FREQA_DS0_MSB _u(2)
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#define ROSC_FREQA_DS0_LSB _u(0)
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#define ROSC_FREQA_DS0_ACCESS "RW"
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// =============================================================================
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// Register : ROSC_FREQB
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// Description : For a detailed description see freqa register
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#define ROSC_FREQB_OFFSET _u(0x00000008)
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#define ROSC_FREQB_BITS _u(0xffff7777)
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#define ROSC_FREQB_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQB_PASSWD
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// Description : Set to 0x9696 to apply the settings
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// Any other value in this field will set all drive strengths to 0
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// 0x9696 -> PASS
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#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
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#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
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#define ROSC_FREQB_PASSWD_MSB _u(31)
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#define ROSC_FREQB_PASSWD_LSB _u(16)
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#define ROSC_FREQB_PASSWD_ACCESS "RW"
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#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQB_DS7
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// Description : Stage 7 drive strength
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#define ROSC_FREQB_DS7_RESET _u(0x0)
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#define ROSC_FREQB_DS7_BITS _u(0x00007000)
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#define ROSC_FREQB_DS7_MSB _u(14)
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#define ROSC_FREQB_DS7_LSB _u(12)
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#define ROSC_FREQB_DS7_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQB_DS6
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// Description : Stage 6 drive strength
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#define ROSC_FREQB_DS6_RESET _u(0x0)
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#define ROSC_FREQB_DS6_BITS _u(0x00000700)
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#define ROSC_FREQB_DS6_MSB _u(10)
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#define ROSC_FREQB_DS6_LSB _u(8)
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#define ROSC_FREQB_DS6_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQB_DS5
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// Description : Stage 5 drive strength
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#define ROSC_FREQB_DS5_RESET _u(0x0)
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#define ROSC_FREQB_DS5_BITS _u(0x00000070)
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#define ROSC_FREQB_DS5_MSB _u(6)
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#define ROSC_FREQB_DS5_LSB _u(4)
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#define ROSC_FREQB_DS5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_FREQB_DS4
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// Description : Stage 4 drive strength
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#define ROSC_FREQB_DS4_RESET _u(0x0)
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#define ROSC_FREQB_DS4_BITS _u(0x00000007)
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#define ROSC_FREQB_DS4_MSB _u(2)
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#define ROSC_FREQB_DS4_LSB _u(0)
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#define ROSC_FREQB_DS4_ACCESS "RW"
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// =============================================================================
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// Register : ROSC_DORMANT
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// Description : Ring Oscillator pause control
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// This is used to save power by pausing the ROSC
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// On power-up this field is initialised to WAKE
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// An invalid write will also select WAKE
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// Warning: setup the irq before selecting dormant mode
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// 0x636f6d61 -> DORMANT
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// 0x77616b65 -> WAKE
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#define ROSC_DORMANT_OFFSET _u(0x0000000c)
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#define ROSC_DORMANT_BITS _u(0xffffffff)
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#define ROSC_DORMANT_RESET "-"
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#define ROSC_DORMANT_MSB _u(31)
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#define ROSC_DORMANT_LSB _u(0)
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#define ROSC_DORMANT_ACCESS "RW"
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#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
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#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
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// =============================================================================
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// Register : ROSC_DIV
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// Description : Controls the output divider
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// set to 0xaa0 + div where
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// div = 0 divides by 32
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// div = 1-31 divides by div
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// any other value sets div=31
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// this register resets to div=16
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// 0xaa0 -> PASS
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#define ROSC_DIV_OFFSET _u(0x00000010)
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#define ROSC_DIV_BITS _u(0x00000fff)
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#define ROSC_DIV_RESET "-"
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#define ROSC_DIV_MSB _u(11)
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#define ROSC_DIV_LSB _u(0)
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#define ROSC_DIV_ACCESS "RW"
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#define ROSC_DIV_VALUE_PASS _u(0xaa0)
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// =============================================================================
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// Register : ROSC_PHASE
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// Description : Controls the phase shifted output
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#define ROSC_PHASE_OFFSET _u(0x00000014)
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#define ROSC_PHASE_BITS _u(0x00000fff)
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#define ROSC_PHASE_RESET _u(0x00000008)
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// -----------------------------------------------------------------------------
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// Field : ROSC_PHASE_PASSWD
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// Description : set to 0xaa
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// any other value enables the output with shift=0
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#define ROSC_PHASE_PASSWD_RESET _u(0x00)
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#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
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#define ROSC_PHASE_PASSWD_MSB _u(11)
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#define ROSC_PHASE_PASSWD_LSB _u(4)
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#define ROSC_PHASE_PASSWD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_PHASE_ENABLE
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// Description : enable the phase-shifted output
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// this can be changed on-the-fly
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#define ROSC_PHASE_ENABLE_RESET _u(0x1)
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#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
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#define ROSC_PHASE_ENABLE_MSB _u(3)
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#define ROSC_PHASE_ENABLE_LSB _u(3)
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#define ROSC_PHASE_ENABLE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_PHASE_FLIP
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// Description : invert the phase-shifted output
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// this is ignored when div=1
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#define ROSC_PHASE_FLIP_RESET _u(0x0)
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#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
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#define ROSC_PHASE_FLIP_MSB _u(2)
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#define ROSC_PHASE_FLIP_LSB _u(2)
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#define ROSC_PHASE_FLIP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ROSC_PHASE_SHIFT
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// Description : phase shift the phase-shifted output by SHIFT input clocks
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// this can be changed on-the-fly
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// must be set to 0 before setting div=1
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#define ROSC_PHASE_SHIFT_RESET _u(0x0)
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#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
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#define ROSC_PHASE_SHIFT_MSB _u(1)
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#define ROSC_PHASE_SHIFT_LSB _u(0)
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#define ROSC_PHASE_SHIFT_ACCESS "RW"
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// =============================================================================
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// Register : ROSC_STATUS
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// Description : Ring Oscillator Status
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#define ROSC_STATUS_OFFSET _u(0x00000018)
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#define ROSC_STATUS_BITS _u(0x81011000)
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#define ROSC_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_STABLE
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// Description : Oscillator is running and stable
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#define ROSC_STATUS_STABLE_RESET _u(0x0)
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#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
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#define ROSC_STATUS_STABLE_MSB _u(31)
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#define ROSC_STATUS_STABLE_LSB _u(31)
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#define ROSC_STATUS_STABLE_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_BADWRITE
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// Description : An invalid value has been written to CTRL_ENABLE or
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// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
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#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
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#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
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#define ROSC_STATUS_BADWRITE_MSB _u(24)
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#define ROSC_STATUS_BADWRITE_LSB _u(24)
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#define ROSC_STATUS_BADWRITE_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_DIV_RUNNING
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// Description : post-divider is running
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// this resets to 0 but transitions to 1 during chip startup
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#define ROSC_STATUS_DIV_RUNNING_RESET "-"
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#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
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#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
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#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
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#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_ENABLED
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// Description : Oscillator is enabled but not necessarily running and stable
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// this resets to 0 but transitions to 1 during chip startup
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#define ROSC_STATUS_ENABLED_RESET "-"
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#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
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#define ROSC_STATUS_ENABLED_MSB _u(12)
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#define ROSC_STATUS_ENABLED_LSB _u(12)
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#define ROSC_STATUS_ENABLED_ACCESS "RO"
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// =============================================================================
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// Register : ROSC_RANDOMBIT
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// Description : This just reads the state of the oscillator output so
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// randomness is compromised if the ring oscillator is stopped or
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// run at a harmonic of the bus frequency
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#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
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#define ROSC_RANDOMBIT_BITS _u(0x00000001)
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#define ROSC_RANDOMBIT_RESET _u(0x00000001)
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#define ROSC_RANDOMBIT_MSB _u(0)
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#define ROSC_RANDOMBIT_LSB _u(0)
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#define ROSC_RANDOMBIT_ACCESS "RO"
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// =============================================================================
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// Register : ROSC_COUNT
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// Description : A down counter running at the ROSC frequency which counts to
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// zero and stops.
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// To start the counter write a non-zero value.
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// Can be used for short software pauses when setting up time
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// sensitive hardware.
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#define ROSC_COUNT_OFFSET _u(0x00000020)
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#define ROSC_COUNT_BITS _u(0x000000ff)
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#define ROSC_COUNT_RESET _u(0x00000000)
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#define ROSC_COUNT_MSB _u(7)
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#define ROSC_COUNT_LSB _u(0)
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#define ROSC_COUNT_ACCESS "RW"
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// =============================================================================
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#endif // HARDWARE_REGS_ROSC_DEFINED
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