mirror of https://github.com/Desuuuu/klipper.git
134 lines
5.1 KiB
C
134 lines
5.1 KiB
C
/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_ADDRESS_MAPPED_H
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#define _HARDWARE_ADDRESS_MAPPED_H
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//#include "pico.h"
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#define __force_inline inline
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#define static_assert(a,b)
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#include "hardware/regs/addressmap.h"
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/** \file address_mapped.h
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* \defgroup hardware_base hardware_base
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*
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* Low-level types and (atomic) accessors for memory-mapped hardware registers
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*
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* `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included
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* by default by all other hardware libraries.
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*
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* The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register.
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* The register type names are formed by concatenating one from each of the 3 parts A, B, C
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* A | B | C | Meaning
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* ------|---|---|--------
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* io_ | | | A Memory mapped IO register
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* |ro_| | read-only access
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* |rw_| | read-write access
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* |wo_| | write-only access (can't actually be enforced via C API)
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* | | 8| 8-bit wide access
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* | | 16| 16-bit wide access
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* | | 32| 32-bit wide access
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*
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* When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write
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* 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`.
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*
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* RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
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* a hardware register so that concurrent access by two cores is always consistent with one atomic operation
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* being performed first, followed by the second.
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*
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* See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register
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*
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* Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can
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* get an alias to the entire structure such that writing any member (register) within the structure is equivalent
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* to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()...
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*
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* For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller,
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* leaving the other bits unchanged.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
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#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
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typedef volatile uint32_t io_rw_32;
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typedef const volatile uint32_t io_ro_32;
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typedef volatile uint32_t io_wo_32;
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typedef volatile uint16_t io_rw_16;
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typedef const volatile uint16_t io_ro_16;
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typedef volatile uint16_t io_wo_16;
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typedef volatile uint8_t io_rw_8;
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typedef const volatile uint8_t io_ro_8;
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typedef volatile uint8_t io_wo_8;
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typedef volatile uint8_t *const ioptr;
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typedef ioptr const const_ioptr;
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// Untyped conversion alias pointer generation macros
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#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr)))
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#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr)))
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#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr)))
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// Typed conversion alias pointer generation macros
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#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
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#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
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#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
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/*! \brief Atomically set the specified bits to 1 in a HW register
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* \ingroup hardware_base
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*
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* \param addr Address of writable register
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* \param mask Bit-mask specifying bits to set
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*/
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__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
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*(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask;
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}
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/*! \brief Atomically clear the specified bits to 0 in a HW register
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* \ingroup hardware_base
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*
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* \param addr Address of writable register
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* \param mask Bit-mask specifying bits to clear
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*/
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__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
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*(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask;
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}
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/*! \brief Atomically flip the specified bits in a HW register
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* \ingroup hardware_base
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*
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* \param addr Address of writable register
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* \param mask Bit-mask specifying bits to invert
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*/
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__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
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*(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask;
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}
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/*! \brief Set new values for a sub-set of the bits in a HW register
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* \ingroup hardware_base
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*
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* Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set
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*
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* Note: this method allows safe concurrent modification of *different* bits of
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* a register, but multiple concurrent access to the same bits is still unsafe.
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*
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* \param addr Address of writable register
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* \param values Bits values
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* \param write_mask Mask of bits to change
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*/
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__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
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hw_xor_bits(addr, (*addr ^ values) & write_mask);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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