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stm32: USB clock source from PLLQCLK on stm32g0 (#5341) 

Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
This commit is contained in:
BIGTREETECH 2022-03-10 02:11:04 +08:00 committed by GitHub
parent c721c20c97
commit d75154d695
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1 changed files with 4 additions and 6 deletions
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10
src/stm32/stm32g0.c
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@ -81,7 +81,8 @@ clock_setup(void)
} }
pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos; pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos;
pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos; pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos;
RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN; pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos;
RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN;
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
// Wait for PLL lock // Wait for PLL lock
@ -95,11 +96,8 @@ clock_setup(void)
// Enable USB clock // Enable USB clock
if (CONFIG_USBSERIAL) { if (CONFIG_USBSERIAL) {
RCC->CR |= RCC_CR_HSI48ON; // PLLQCLK
while (!(RCC->CR & RCC_CR_HSI48RDY)) RCC->CCIPR2 |= RCC_CCIPR2_USBSEL_1;
;
enable_pclock(CRS_BASE);
CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
} }
} }