From ccaf58a02cf132cb43ad3f45f5200841044f66a8 Mon Sep 17 00:00:00 2001 From: Matt Shepcar Date: Sun, 24 Jan 2021 15:24:11 +0000 Subject: [PATCH] stm32f1: Fix for using 16MHz external crystal (#3814) Signed-off-by: Matt Shepcar --- src/stm32/stm32f1.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index a1c4c7fe..886b7b91 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -162,9 +162,14 @@ clock_setup(void) uint32_t cfgr; if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { // Configure 72Mhz PLL from external crystal (HSE) - uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ; RCC->CR |= RCC_CR_HSEON; - cfgr = (1 << RCC_CFGR_PLLSRC_Pos) | ((div - 2) << RCC_CFGR_PLLMULL_Pos); + uint32_t div = CONFIG_CLOCK_FREQ / (CONFIG_CLOCK_REF_FREQ / 2); + cfgr = 1 << RCC_CFGR_PLLSRC_Pos; + if ((div & 1) && div <= 16) + cfgr |= RCC_CFGR_PLLXTPRE_HSE_DIV2; + else + div /= 2; + cfgr |= (div - 2) << RCC_CFGR_PLLMULL_Pos; } else { // Configure 72Mhz PLL from internal 8Mhz oscillator (HSI) uint32_t div2 = (CONFIG_CLOCK_FREQ / 8000000) * 2;