mirror of https://github.com/Desuuuu/klipper.git
stm32: add FDCAN support for STM32H743 (SKR-3 Series) (#5668)
Signed-off-by: Chen.BJ from BigTreeTech <chenbj@biqu3d.com>
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@ -107,7 +107,7 @@ config HAVE_STM32_CANBUS
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default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
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default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
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config HAVE_STM32_FDCANBUS
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config HAVE_STM32_FDCANBUS
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bool
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bool
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default y if MACH_STM32G0
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default y if MACH_STM32G0 || MACH_STM32H7
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config HAVE_STM32_USBCANBUS
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config HAVE_STM32_USBCANBUS
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bool
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bool
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depends on HAVE_STM32_USBFS || HAVE_STM32_USBOTG
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depends on HAVE_STM32_USBFS || HAVE_STM32_USBOTG
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@ -351,12 +351,20 @@ choice
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select CANSERIAL
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select CANSERIAL
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config STM32_MMENU_CANBUS_PD0_PD1
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config STM32_MMENU_CANBUS_PD0_PD1
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bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS
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bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS
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depends on HAVE_STM32_CANBUS
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depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS
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select CANSERIAL
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select CANSERIAL
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config STM32_MMENU_CANBUS_PB0_PB1
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config STM32_MMENU_CANBUS_PB0_PB1
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bool "CAN bus (on PB0/PB1)"
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bool "CAN bus (on PB0/PB1)"
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depends on HAVE_STM32_FDCANBUS
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depends on HAVE_STM32_FDCANBUS
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select CANSERIAL
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select CANSERIAL
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config STM32_MMENU_CANBUS_PD12_PD13
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bool "CAN bus (on PD12/PD13)"
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depends on HAVE_STM32_FDCANBUS
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select CANSERIAL
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config STM32_MMENU_CANBUS_PC2_PC3
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bool "CAN bus (on PC2/PC3)"
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depends on HAVE_STM32_FDCANBUS
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select CANSERIAL
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config STM32_USBCANBUS_PA11_PA12
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config STM32_USBCANBUS_PA11_PA12
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bool "USB to CAN bus bridge (USB on PA11/PA12)"
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bool "USB to CAN bus bridge (USB on PA11/PA12)"
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depends on HAVE_STM32_USBCANBUS
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depends on HAVE_STM32_USBCANBUS
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@ -377,10 +385,16 @@ choice
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depends on HAVE_STM32_CANBUS && MACH_STM32F4
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depends on HAVE_STM32_CANBUS && MACH_STM32F4
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config STM32_CMENU_CANBUS_PD0_PD1
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config STM32_CMENU_CANBUS_PD0_PD1
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bool "CAN bus (on PD0/PD1)"
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bool "CAN bus (on PD0/PD1)"
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depends on HAVE_STM32_CANBUS
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depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS
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config STM32_CMENU_CANBUS_PB0_PB1
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config STM32_CMENU_CANBUS_PB0_PB1
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bool "CAN bus (on PB0/PB1)"
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bool "CAN bus (on PB0/PB1)"
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depends on HAVE_STM32_FDCANBUS
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depends on HAVE_STM32_FDCANBUS
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config STM32_CMENU_CANBUS_PD12_PD13
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bool "CAN bus (on PD12/PD13)"
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depends on HAVE_STM32_FDCANBUS
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config STM32_CMENU_CANBUS_PC2_PC3
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bool "CAN bus (on PC2/PC3)"
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depends on HAVE_STM32_FDCANBUS
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endchoice
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endchoice
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@ -402,5 +416,11 @@ config STM32_CANBUS_PD0_PD1
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config STM32_CANBUS_PB0_PB1
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config STM32_CANBUS_PB0_PB1
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bool
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bool
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default y if STM32_MMENU_CANBUS_PB0_PB1 || STM32_CMENU_CANBUS_PB0_PB1
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default y if STM32_MMENU_CANBUS_PB0_PB1 || STM32_CMENU_CANBUS_PB0_PB1
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config STM32_CANBUS_PD12_PD13
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bool
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default y if STM32_MMENU_CANBUS_PD12_PD13 || STM32_CMENU_CANBUS_PD12_PD13
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config STM32_CANBUS_PC2_PC3
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bool
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default y if STM32_MMENU_CANBUS_PC2_PC3 || STM32_CMENU_CANBUS_PC2_PC3
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endif
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endif
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@ -55,13 +55,25 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9");
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9");
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#define GPIO_Rx GPIO('B', 8)
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#define GPIO_Rx GPIO('B', 8)
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#define GPIO_Tx GPIO('B', 9)
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#define GPIO_Tx GPIO('B', 9)
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#elif CONFIG_STM32_CANBUS_PD0_PD1
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PD0,PD1");
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#define GPIO_Rx GPIO('D', 0)
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#define GPIO_Tx GPIO('D', 1)
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#elif CONFIG_STM32_CANBUS_PD12_PD13
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PD12,PD13");
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#define GPIO_Rx GPIO('D', 12)
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#define GPIO_Tx GPIO('D', 13)
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#elif CONFIG_STM32_CANBUS_PB0_PB1
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#elif CONFIG_STM32_CANBUS_PB0_PB1
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1");
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1");
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#define GPIO_Rx GPIO('B', 0)
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#define GPIO_Rx GPIO('B', 0)
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#define GPIO_Tx GPIO('B', 1)
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#define GPIO_Tx GPIO('B', 1)
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#elif CONFIG_STM32_CANBUS_PC2_PC3
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3");
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#define GPIO_Rx GPIO('C', 2)
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#define GPIO_Tx GPIO('C', 3)
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#endif
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#endif
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#if !CONFIG_STM32_CANBUS_PB0_PB1
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#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3)
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#define SOC_CAN FDCAN1
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#define SOC_CAN FDCAN1
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#define MSG_RAM fdcan_ram->fdcan1
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#define MSG_RAM fdcan_ram->fdcan1
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#else
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#else
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@ -69,8 +81,13 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
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#define MSG_RAM fdcan_ram->fdcan2
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#define MSG_RAM fdcan_ram->fdcan2
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#endif
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#endif
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#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
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#if CONFIG_MACH_STM32G0
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#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
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#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
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#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
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#elif CONFIG_MACH_STM32H7
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#define CAN_IT0_IRQn FDCAN1_IT0_IRQn
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#define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number
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#endif
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#ifndef SOC_CAN
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#ifndef SOC_CAN
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#error No known CAN device for configured MCU
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#error No known CAN device for configured MCU
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@ -128,8 +145,14 @@ canbus_set_filter(uint32_t id)
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can_filter(0, CANBUS_ID_ADMIN);
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can_filter(0, CANBUS_ID_ADMIN);
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can_filter(1, id);
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can_filter(1, id);
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can_filter(2, id + 1);
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can_filter(2, id + 1);
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#if CONFIG_MACH_STM32G0
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SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
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SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
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| 0x02 << FDCAN_RXGFC_ANFS_Pos);
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| 0x02 << FDCAN_RXGFC_ANFS_Pos);
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#elif CONFIG_MACH_STM32H7
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SOC_CAN->SIDFC |= (id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos;
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SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos;
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#endif
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/* Leave the initialisation mode for the filter */
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/* Leave the initialisation mode for the filter */
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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@ -251,6 +274,29 @@ can_init(void)
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SOC_CAN->NBTP = btr;
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SOC_CAN->NBTP = btr;
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#if CONFIG_MACH_STM32H7
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/*
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The Message RAM of STM32H7 is settable
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So we set it to be consistent with STM32G0
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*/
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uint32_t flssa = (uint32_t)&MSG_RAM - (uint32_t)&fdcan_ram->fdcan1;
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uint32_t f0sa = flssa +
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(((uint32_t)MSG_RAM.RXF0 - (uint32_t)MSG_RAM.FLS) / 4);
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uint32_t tbsa = f0sa +
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(((uint32_t)MSG_RAM.TXFIFO - (uint32_t)MSG_RAM.RXF0) / 4);
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SOC_CAN->SIDFC = flssa << FDCAN_SIDFC_FLSSA_Pos;
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SOC_CAN->RXF0C = ((f0sa << FDCAN_RXF0C_F0SA_Pos)
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| (3 << FDCAN_RXF0C_F0S_Pos));
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SOC_CAN->RXESC = ((7 << FDCAN_RXESC_F1DS_Pos)
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| (7 << FDCAN_RXESC_F0DS_Pos));
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SOC_CAN->TXBC = ((tbsa << FDCAN_TXBC_TBSA_Pos)
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| (3 << FDCAN_TXBC_TFQS_Pos));
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SOC_CAN->TXESC = 7 << FDCAN_TXESC_TBDS_Pos;
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#endif
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/* Leave the initialisation mode */
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/* Leave the initialisation mode */
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT;
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@ -46,8 +46,16 @@ lookup_clock_line(uint32_t periph_base)
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uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400);
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uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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} else {
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uint32_t bit = 1 << ((periph_base - D2_APB1PERIPH_BASE) / 0x400);
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uint32_t offset = ((periph_base - D2_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB1LENR,.rst=&RCC->APB1LRSTR,.bit=bit};
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if (offset < 32) {
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uint32_t bit = 1 << offset;
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return (struct cline){
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.en=&RCC->APB1LENR, .rst=&RCC->APB1LRSTR, .bit=bit};
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} else {
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uint32_t bit = 1 << (offset - 32);
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return (struct cline){
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.en=&RCC->APB1HENR, .rst=&RCC->APB1HRSTR, .bit=bit};
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}
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}
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}
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}
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}
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@ -170,6 +178,9 @@ clock_setup(void)
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
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;
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;
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// Set the source of FDCAN clock
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MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, RCC_D2CCIP1R_FDCANSEL_0);
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// Configure HSI48 clock for USB
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// Configure HSI48 clock for USB
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if (CONFIG_USB) {
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if (CONFIG_USB) {
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SET_BIT(RCC->CR, RCC_CR_HSI48ON);
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SET_BIT(RCC->CR, RCC_CR_HSI48ON);
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