mirror of https://github.com/Desuuuu/klipper.git
stm32: Add support for USB on stm32g0
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
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@ -93,7 +93,7 @@ config MACH_STM32F4x5 # F405, F407, F429 series
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bool
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bool
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config HAVE_STM32_USBFS
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config HAVE_STM32_USBFS
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bool
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bool
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default y if MACH_STM32F103 || MACH_STM32F0x2 || MACH_STM32F070
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default y if MACH_STM32F103 || MACH_STM32F0x2 || MACH_STM32F070 || MACH_STM32G0
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config HAVE_STM32_USBOTG
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config HAVE_STM32_USBOTG
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bool
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bool
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default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7
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default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7
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@ -1,4 +1,4 @@
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// Hardware interface to "fullspeed USB controller" on stm32f1
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// Hardware interface to "fullspeed USB controller"
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//
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//
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// Copyright (C) 2018-2021 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2018-2021 Kevin O'Connor <kevin@koconnor.net>
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//
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//
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@ -18,11 +18,29 @@
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#if CONFIG_MACH_STM32F103
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#if CONFIG_MACH_STM32F103
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// Transfer memory is accessed with 32bits, but contains only 16bits of data
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// Transfer memory is accessed with 32bits, but contains only 16bits of data
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typedef volatile uint32_t epmword_t;
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typedef volatile uint32_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_LP_IRQn
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#define USBx_IRQn USB_LP_IRQn
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#elif CONFIG_MACH_STM32F0
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#elif CONFIG_MACH_STM32F0
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// Transfer memory is accessed with 16bits and contains 16bits of data
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// Transfer memory is accessed with 16bits and contains 16bits of data
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typedef volatile uint16_t epmword_t;
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typedef volatile uint16_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_IRQn
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#define USBx_IRQn USB_IRQn
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#elif CONFIG_MACH_STM32G0
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// Transfer memory is accessed with 32bits and contains 32bits of data
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typedef volatile uint32_t epmword_t;
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#define WSIZE 4
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#define USBx_IRQn USB_UCPD1_2_IRQn
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// The stm32g0 has slightly different register names
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#define USB USB_DRD_FS
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#define USB_PMAADDR USB_DRD_PMAADDR
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#define USB_EPADDR_FIELD USB_CHEP_ADDR
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#define USB_EP_CTR_RX USB_EP_VTRX
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#define USB_EP_CTR_TX USB_EP_VTTX
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#define USB_EPRX_STAT USB_EP_RX_STRX
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#define USB_EPTX_STAT USB_EP_TX_STTX
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#define USB_ISTR_EP_ID USB_ISTR_IDN
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#define USB_CNTR_FRES USB_CNTR_USBRST
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#endif
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#endif
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@ -32,9 +50,9 @@
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// Layout of the USB transfer memory
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// Layout of the USB transfer memory
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#define EPM ((epmword_t*)USB_PMAADDR)
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#define EPM ((epmword_t*)USB_PMAADDR)
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#define EPM_EP_DESC(ep) (&EPM[(ep) * 4])
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#define EPM_EP_DESC(ep) (&EPM[(ep) * (8 / WSIZE)])
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#define EPM_BUF_OFFSET 0x10
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#define EPM_BUF_OFFSET 0x10
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#define EPM_EP_BUF_SIZE (64 / 2 + 1)
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#define EPM_EP_BUF_SIZE (64 / WSIZE + 1)
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#define EPM_EP_TX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (ep)*2*EPM_EP_BUF_SIZE])
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#define EPM_EP_TX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (ep)*2*EPM_EP_BUF_SIZE])
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#define EPM_EP_RX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (1+(ep)*2)*EPM_EP_BUF_SIZE])
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#define EPM_EP_RX_BUF(ep) (&EPM[EPM_BUF_OFFSET + (1+(ep)*2)*EPM_EP_BUF_SIZE])
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@ -42,15 +60,20 @@
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static void
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static void
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epm_ep_desc_setup(int ep, int rx_size)
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epm_ep_desc_setup(int ep, int rx_size)
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{
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{
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uint32_t addr_tx = (EPM_EP_TX_BUF(ep) - EPM) * 2, count_tx = 0;
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uint32_t addr_tx = (EPM_EP_TX_BUF(ep) - EPM) * WSIZE, count_tx = 0;
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uint32_t addr_rx = (EPM_EP_RX_BUF(ep) - EPM) * 2;
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uint32_t addr_rx = (EPM_EP_RX_BUF(ep) - EPM) * WSIZE;
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uint32_t count_rx = (rx_size <= 30 ? DIV_ROUND_UP(rx_size, 2) << 10
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uint32_t count_rx = (rx_size <= 30 ? DIV_ROUND_UP(rx_size, 2) << 10
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: ((DIV_ROUND_UP(rx_size, 32) - 1) << 10) | 0x8000);
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: ((DIV_ROUND_UP(rx_size, 32) - 1) << 10) | 0x8000);
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep);
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desc[0] = addr_tx;
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if (WSIZE == 2) {
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desc[1] = count_tx;
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desc[0] = addr_tx;
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desc[2] = addr_rx;
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desc[1] = count_tx;
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desc[3] = count_rx;
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desc[2] = addr_rx;
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desc[3] = count_rx;
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} else {
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desc[0] = addr_tx | (count_tx << 16);
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desc[1] = addr_rx | (count_rx << 16);
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}
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}
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}
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// Return number of read bytes on an rx endpoint
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// Return number of read bytes on an rx endpoint
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@ -58,7 +81,9 @@ static uint32_t
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epm_get_ep_count_rx(int ep)
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epm_get_ep_count_rx(int ep)
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{
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{
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep);
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return desc[3] & 0x3ff;
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if (WSIZE == 2)
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return desc[3] & 0x3ff;
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return (desc[1] >> 16) & 0x3ff;
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}
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}
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// Set number of bytes ready to be transmitted on a tx endpoint
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// Set number of bytes ready to be transmitted on a tx endpoint
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@ -66,7 +91,12 @@ static void
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epm_set_ep_count_tx(int ep, uint32_t count)
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epm_set_ep_count_tx(int ep, uint32_t count)
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{
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{
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epmword_t *desc = EPM_EP_DESC(ep);
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epmword_t *desc = EPM_EP_DESC(ep);
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desc[1] = count;
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if (WSIZE == 2) {
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desc[1] = count;
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} else {
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uint32_t addr_tx = (EPM_EP_TX_BUF(ep) - EPM) * WSIZE;
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desc[0] = addr_tx | (count << 16);
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}
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}
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}
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// Setup the transfer descriptors in dedicated usb memory
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// Setup the transfer descriptors in dedicated usb memory
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@ -88,13 +118,23 @@ btable_read_packet(int ep, uint8_t *dest, int max_len)
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if (count > max_len)
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if (count > max_len)
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count = max_len;
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count = max_len;
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int i;
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int i;
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for (i=0; i<(count/2); i++) {
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for (i=0; i<count/WSIZE; i++) {
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uint32_t d = *src++;
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uint32_t d = *src++;
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*dest++ = d;
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*dest++ = d;
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*dest++ = d >> 8;
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*dest++ = d >> 8;
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if (WSIZE == 4) {
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*dest++ = d >> 16;
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*dest++ = d >> 24;
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}
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}
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if (count & (WSIZE-1)) {
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uint32_t d = *src;
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*dest++ = d;
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if ((count & (WSIZE-1)) > 1)
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*dest++ = d >> 8;
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if ((count & (WSIZE-1)) > 2)
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*dest++ = d >> 16;
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}
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}
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if (count & 1)
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*dest = *src;
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return count;
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return count;
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}
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}
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@ -104,12 +144,22 @@ btable_write_packet(int ep, const uint8_t *src, int count)
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{
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{
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epmword_t *dest = EPM_EP_TX_BUF(ep);
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epmword_t *dest = EPM_EP_TX_BUF(ep);
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int i;
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int i;
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for (i=0; i<(count/2); i++) {
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for (i=0; i<count/WSIZE; i++) {
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uint8_t b1 = *src++, b2 = *src++;
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uint8_t b1 = *src++, b2 = *src++, b3 = 0, b4 = 0;
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*dest++ = b1 | (b2 << 8);
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if (WSIZE == 4) {
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b3 = *src++;
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b4 = *src++;
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}
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*dest++ = b1 | (b2 << 8) | (b3 << 16) | (b4 << 24);
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}
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if (count & (WSIZE-1)) {
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uint32_t d = *src++;
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if ((count & (WSIZE-1)) > 1)
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d |= *src++ << 8;
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if ((count & (WSIZE-1)) > 2)
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d |= *src++ << 16;
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*dest = d;
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}
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}
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if (count & 1)
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*dest = *src;
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epm_set_ep_count_tx(ep, count);
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epm_set_ep_count_tx(ep, count);
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}
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}
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@ -302,7 +352,6 @@ usb_init(void)
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// Reset usb controller and enable interrupts
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// Reset usb controller and enable interrupts
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USB->CNTR = USB_CNTR_FRES;
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USB->CNTR = USB_CNTR_FRES;
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USB->BTABLE = 0;
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USB->DADDR = 0;
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USB->DADDR = 0;
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USB->CNTR = USB_CNTR_RESETM;
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USB->CNTR = USB_CNTR_RESETM;
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USB->ISTR = 0;
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USB->ISTR = 0;
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