lpc176x: Use full peripheral clock speed; fix UART interface

Commit ae89a659 caused a regression in the lpc176x UART handling.
After that commit the UART clock divisor would need to be 6.25 on
lpc1768 or 7.5 on lpc1769, but the code only supports whole numbers.

Set the PCLKSELx registers at startup and return to using full speed
peripheral clocks.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

lib/lpc176x/device/system_LPC17xx.c

@@ -308,8 +308,8 @@
 #define CCLKCFG_Val           0x00000002
 #define USBCLKCFG_Val         0x00000000
 
-#define PCLKSEL0_Val          0x00000000
-#define PCLKSEL1_Val          0x00000000
+#define PCLKSEL0_Val          0x55515155
+#define PCLKSEL1_Val          0x54555455
 #define PCONP_Val             0x042887DE
 #define CLKOUTCFG_Val         0x00000000
 

lib/lpc176x/lpc176x.patch

@@ -1,6 +1,6 @@
 --- device/system_LPC17xx.c	2018-05-02 12:23:57.292132454 -0400
-+++ device/system_LPC17xx.c	2018-05-23 20:09:29.681308483 -0400
-@@ -297,19 +297,16 @@
++++ device/system_LPC17xx.c	2021-05-04 10:08:17.637502030 -0400
+@@ -297,22 +297,19 @@
  #define CLKSRCSEL_Val         0x00000001
  #define PLL0_SETUP            1
  
@@ -26,5 +26,10 @@
 +#define CCLKCFG_Val           0x00000002
 +#define USBCLKCFG_Val         0x00000000
  
- #define PCLKSEL0_Val          0x00000000
- #define PCLKSEL1_Val          0x00000000
+-#define PCLKSEL0_Val          0x00000000
+-#define PCLKSEL1_Val          0x00000000
++#define PCLKSEL0_Val          0x55515155
++#define PCLKSEL1_Val          0x54555455
+ #define PCONP_Val             0x042887DE
+ #define CLKOUTCFG_Val         0x00000000
+ 

src/lpc176x/main.c

@@ -55,7 +55,7 @@ enable_pclock(uint32_t pclk)
 uint32_t
 get_pclock_frequency(uint32_t pclk)
 {
-    return CONFIG_CLOCK_FREQ / 4;
+    return CONFIG_CLOCK_FREQ;
 }
 
 // Main entry point - called from armcm_boot.c:ResetHandler()