mirror of https://github.com/Desuuuu/klipper.git
stm32: Add stm32h7 SPI support (#4850)
Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
This commit is contained in:
adelyser
GitHub
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3ac354088a
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@ -43,7 +43,9 @@ src-$(CONFIG_MACH_STM32F4) += stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32H7) += ../lib/stm32h7/system_stm32h7xx.c
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src-$(CONFIG_MACH_STM32H7) += stm32/stm32h7.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32H7) += stm32/stm32h7_adc.c
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src-$(CONFIG_HAVE_GPIO_SPI) += stm32/spi.c
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spi-src-y := stm32/spi.c
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spi-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_spi.c
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src-$(CONFIG_HAVE_GPIO_SPI) += $(spi-src-y)
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usb-src-$(CONFIG_HAVE_STM32_USBFS) := stm32/usbfs.c
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usb-src-$(CONFIG_HAVE_STM32_USBOTG) := stm32/usbotg.c
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src-$(CONFIG_USBSERIAL) += $(usb-src-y) stm32/chipid.c generic/usb_cdc.c
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@ -5,7 +5,7 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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// USB and I2C is not supported, SPI is untested!
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// I2C is not supported
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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@ -170,7 +170,10 @@ clock_setup(void)
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2);
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// Disable unused PLL1 outputs
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0);
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN_Msk, 0);
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// Enable PLL1Q and set to 100MHz for SPI 1,2,3
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN, RCC_PLLCFGR_DIVQ1EN);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1,
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(pll_freq / FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos);
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// This is necessary, default is not 1!
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN);
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// Set multiplier DIVN1 and post divider DIVP1
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@ -184,6 +187,7 @@ clock_setup(void)
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS);
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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// Enable VOS0 (overdrive)
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if (CONFIG_CLOCK_FREQ > 400000000) {
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RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
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@ -0,0 +1,150 @@
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// SPI functions on STM32H7
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/io.h" // readb, writeb
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#include "command.h" // shutdown
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#include "gpio.h" // spi_setup
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#include "internal.h" // gpio_peripheral
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#include "sched.h" // sched_shutdown
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struct spi_info {
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SPI_TypeDef *spi;
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uint8_t miso_pin, mosi_pin, sck_pin, function;
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};
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DECL_ENUMERATION("spi_bus", "spi2", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi2", "PB14,PB15,PB13");
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DECL_ENUMERATION("spi_bus", "spi1", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi1", "PA6,PA7,PA5");
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DECL_ENUMERATION("spi_bus", "spi1a", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi1a", "PB4,PB5,PB3");
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#if !CONFIG_MACH_STM32F1
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DECL_ENUMERATION("spi_bus", "spi2a", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi2a", "PC2,PC3,PB10");
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#endif
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#ifdef SPI3
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DECL_ENUMERATION("spi_bus", "spi3", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi3", "PB4,PB5,PB3");
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DECL_ENUMERATION("spi_bus", "spi3a", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi3a", "PC11,PC12,PC10");
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#endif
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#ifdef SPI4
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DECL_ENUMERATION("spi_bus", "spi4", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi4", "PE13,PE14,PE12");
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#endif
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#ifdef GPIOI
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DECL_ENUMERATION("spi_bus", "spi2b", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi2b", "PI2,PI3,PI1");
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#endif
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#ifdef SPI5
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DECL_ENUMERATION("spi_bus", "spi5", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi5", "PF8,PF9,PF7");
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DECL_ENUMERATION("spi_bus", "spi5a", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi5a", "PH7,PF11,PH6");
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#endif
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#ifdef SPI6
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DECL_ENUMERATION("spi_bus", "spi6", __COUNTER__);
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DECL_CONSTANT_STR("BUS_PINS_spi6", "PG12,PG14,PG13");
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#endif
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static const struct spi_info spi_bus[] = {
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{ SPI2, GPIO('B', 14), GPIO('B', 15), GPIO('B', 13), GPIO_FUNCTION(5) },
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{ SPI1, GPIO('A', 6), GPIO('A', 7), GPIO('A', 5), GPIO_FUNCTION(5) },
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{ SPI1, GPIO('B', 4), GPIO('B', 5), GPIO('B', 3), GPIO_FUNCTION(5) },
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#if !CONFIG_MACH_STM32F1
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{ SPI2, GPIO('C', 2), GPIO('C', 3), GPIO('B', 10), GPIO_FUNCTION(5) },
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#endif
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#ifdef SPI3
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{ SPI3, GPIO('B', 4), GPIO('B', 5), GPIO('B', 3), GPIO_FUNCTION(6) },
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{ SPI3, GPIO('C', 11), GPIO('C', 12), GPIO('C', 10), GPIO_FUNCTION(6) },
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#endif
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#ifdef SPI4
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{ SPI4, GPIO('E', 13), GPIO('E', 14), GPIO('E', 12), GPIO_FUNCTION(5) },
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#endif
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{ SPI2, GPIO('I', 2), GPIO('I', 3), GPIO('I', 1), GPIO_FUNCTION(5) },
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#ifdef SPI5
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{ SPI5, GPIO('F', 8), GPIO('F', 9), GPIO('F', 7), GPIO_FUNCTION(5) },
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{ SPI5, GPIO('H', 7), GPIO('F', 11), GPIO('H', 6), GPIO_FUNCTION(5) },
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#endif
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#ifdef SPI6
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{ SPI6, GPIO('G', 12), GPIO('G', 14), GPIO('G', 13), GPIO_FUNCTION(5)},
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#endif
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};
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struct spi_config
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spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
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{
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if (bus >= ARRAY_SIZE(spi_bus))
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shutdown("Invalid spi bus");
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// Enable SPI
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SPI_TypeDef *spi = spi_bus[bus].spi;
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if (!is_enabled_pclock((uint32_t)spi)) {
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enable_pclock((uint32_t)spi);
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gpio_peripheral(spi_bus[bus].miso_pin, spi_bus[bus].function, 1);
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gpio_peripheral(spi_bus[bus].mosi_pin, spi_bus[bus].function, 0);
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gpio_peripheral(spi_bus[bus].sck_pin, spi_bus[bus].function, 0);
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}
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// Calculate CR1 register
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uint32_t pclk = get_pclock_frequency((uint32_t)spi);
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uint32_t div = 0;
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while ((pclk >> (div + 1)) > rate && div < 7)
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div++;
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uint32_t cr1 = SPI_CR1_SPE;
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spi->CFG1 |= (div << SPI_CFG1_MBR_Pos) | (7 << SPI_CFG1_DSIZE_Pos);
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CLEAR_BIT(spi->CFG1, SPI_CFG1_CRCSIZE);
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spi->CFG2 |= ((mode << SPI_CFG2_CPHA_Pos) | SPI_CFG2_MASTER | SPI_CFG2_SSM
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| SPI_CFG2_AFCNTR | SPI_CFG2_SSOE);
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spi->CR1 |= SPI_CR1_SSI;
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return (struct spi_config){ .spi = spi, .spi_cr1 = cr1 };
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}
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void
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spi_prepare(struct spi_config config)
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{
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}
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void
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spi_transfer(struct spi_config config, uint8_t receive_data,
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uint8_t len, uint8_t *data)
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{
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uint8_t rdata = 0;
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SPI_TypeDef *spi = config.spi;
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MODIFY_REG(spi->CR2, SPI_CR2_TSIZE, len);
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// Enable SPI and start transfer, these MUST be set in this sequence
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SET_BIT(spi->CR1, SPI_CR1_SPE);
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SET_BIT(spi->CR1, SPI_CR1_CSTART);
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while (len--) {
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writeb((void *)&spi->TXDR, *data);
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while((spi->SR & (SPI_SR_RXWNE | SPI_SR_RXPLVL)) == 0);
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rdata = readb((void *)&spi->RXDR);
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if (receive_data) {
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*data = rdata;
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}
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data++;
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}
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while ((spi->SR & SPI_SR_EOT) == 0);
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// Clear flags and disable SPI
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SET_BIT(spi->IFCR, 0xFFFFFFFF);
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CLEAR_BIT(spi->CR1, SPI_CR1_SPE);
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}
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