mirror of https://github.com/Desuuuu/klipper.git
lib: Update to the latest can2040 code
Rename to "match" state machine instead of "ack". Minor simplification to tx_note_crc_start(). Call pio_match_clear() from report functions. Add pio_match_calc_key() helper function. Raise irq after 6 passive eof bits for faster rx message notification. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
24a1b50e51
commit
36887ce6fe
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@ -131,4 +131,4 @@ used to upload firmware to devices flashed with the CanBoot bootloader.
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The can2040 directory contains code from:
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https://github.com/KevinOConnor/can2040
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revision 17b8ace15584077cd0bf0c3e038c2a2a8edd70ed.
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revision c981fa7666ee9ce1650904e38f7287cb861df18c.
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@ -74,8 +74,8 @@ rp2040_gpio_peripheral(uint32_t gpio, int func, int pull_up)
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#define can2040_offset_sync_end 13u
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#define can2040_offset_shared_rx_read 13u
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#define can2040_offset_shared_rx_end 15u
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#define can2040_offset_ack_no_match 18u
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#define can2040_offset_ack_end 25u
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#define can2040_offset_match_load_next 18u
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#define can2040_offset_match_end 25u
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#define can2040_offset_tx_got_recessive 25u
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#define can2040_offset_tx_start 26u
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#define can2040_offset_tx_conflict 31u
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@ -152,21 +152,21 @@ pio_rx_setup(struct can2040 *cd)
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sm->instr = can2040_offset_shared_rx_read; // jmp shared_rx_read
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}
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// Setup PIO "ack" state machine (state machine 2)
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// Setup PIO "match" state machine (state machine 2)
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static void
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pio_ack_setup(struct can2040 *cd)
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pio_match_setup(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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struct pio_sm_hw *sm = &pio_hw->sm[2];
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sm->execctrl = (
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(can2040_offset_ack_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
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(can2040_offset_match_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
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| can2040_offset_shared_rx_read << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB);
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sm->pinctrl = cd->gpio_rx << PIO_SM0_PINCTRL_IN_BASE_LSB;
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sm->shiftctrl = 0;
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sm->instr = 0xe040; // set y, 0
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sm->instr = 0xa0e2; // mov osr, y
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sm->instr = 0xa02a, // mov x, !y
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sm->instr = can2040_offset_ack_no_match; // jmp ack_no_match
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sm->instr = can2040_offset_match_load_next; // jmp match_load_next
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}
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// Setup PIO "tx" state machine (state machine 3)
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@ -186,12 +186,60 @@ pio_tx_setup(struct can2040 *cd)
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sm->instr = 0xe081; // set pindirs, 1
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}
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// Check if the PIO "tx" state machine stopped due to passive/dominant conflict
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static int
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pio_tx_did_conflict(struct can2040 *cd)
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// Set PIO "sync" machine to signal "may transmit" (sm irq 0) on 11 idle bits
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static void
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pio_sync_normal_start_signal(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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return pio_hw->sm[3].addr == can2040_offset_tx_conflict;
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uint32_t eom_idx = can2040_offset_sync_found_end_of_message;
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pio_hw->instr_mem[eom_idx] = 0xe13a; // set x, 26 [1]
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}
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// Set PIO "sync" machine to signal "may transmit" (sm irq 0) on 17 idle bits
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static void
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pio_sync_slow_start_signal(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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uint32_t eom_idx = can2040_offset_sync_found_end_of_message;
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pio_hw->instr_mem[eom_idx] = 0xa127; // mov x, osr [1]
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}
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// Test if PIO "rx" state machine has overflowed its fifos
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static int
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pio_rx_check_stall(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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return pio_hw->fdebug & (1 << (PIO_FDEBUG_RXSTALL_LSB + 1));
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}
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// Report number of bytes still pending in PIO "rx" fifo queue
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static int
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pio_rx_fifo_level(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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return (pio_hw->flevel & PIO_FLEVEL_RX1_BITS) >> PIO_FLEVEL_RX1_LSB;
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}
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// Set PIO "match" state machine to raise a "matched" signal on a bit sequence
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static void
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pio_match_check(struct can2040 *cd, uint32_t match_key)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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pio_hw->txf[2] = match_key;
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}
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// Calculate pos+bits identifier for PIO "match" state machine
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static uint32_t
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pio_match_calc_key(uint32_t raw_bits, uint32_t rx_bit_pos)
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{
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return (raw_bits & 0x1fffff) | ((-rx_bit_pos) << 21);
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}
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// Cancel any pending checks on PIO "match" state machine
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static void
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pio_match_clear(struct can2040 *cd)
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{
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pio_match_check(cd, 0);
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}
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// Flush and halt PIO "tx" state machine
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@ -201,12 +249,13 @@ pio_tx_reset(struct can2040 *cd)
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pio_hw_t *pio_hw = cd->pio_hw;
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pio_hw->ctrl = ((0x07 << PIO_CTRL_SM_ENABLE_LSB)
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| (0x08 << PIO_CTRL_SM_RESTART_LSB));
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pio_hw->irq = (1 << 2) | (1<< 3); // clear irq 2 and 3
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pio_hw->irq = (1 << 2) | (1<< 3); // clear "matched" and "ack done" signals
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// Clear tx fifo
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struct pio_sm_hw *sm = &pio_hw->sm[3];
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sm->shiftctrl = 0;
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sm->shiftctrl = (PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS
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| PIO_SM0_SHIFTCTRL_AUTOPULL_BITS);
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// Must reset again after clearing fifo
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pio_hw->ctrl = ((0x07 << PIO_CTRL_SM_ENABLE_LSB)
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| (0x08 << PIO_CTRL_SM_RESTART_LSB));
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}
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@ -228,18 +277,9 @@ pio_tx_send(struct can2040 *cd, uint32_t *data, uint32_t count)
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pio_hw->ctrl = 0x0f << PIO_CTRL_SM_ENABLE_LSB;
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}
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// Set PIO "ack" state machine to check a given CRC sequence
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// Set PIO "tx" state machine to inject an ack after a CRC match
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static void
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pio_ack_check(struct can2040 *cd, uint32_t crc_bits, uint32_t rx_bit_pos)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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uint32_t key = (crc_bits & 0x1fffff) | ((-rx_bit_pos) << 21);
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pio_hw->txf[2] = key;
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}
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// Set PIO "ack" state machine to check a CRC and inject an ack on success
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static void
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pio_ack_inject(struct can2040 *cd, uint32_t crc_bits, uint32_t rx_bit_pos)
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pio_tx_inject_ack(struct can2040 *cd, uint32_t match_key)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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pio_tx_reset(cd);
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@ -251,34 +291,18 @@ pio_ack_inject(struct can2040 *cd, uint32_t crc_bits, uint32_t rx_bit_pos)
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sm->instr = 0x20c2; // wait 1 irq, 2
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pio_hw->ctrl = 0x0f << PIO_CTRL_SM_ENABLE_LSB;
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pio_ack_check(cd, crc_bits, rx_bit_pos);
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pio_match_check(cd, match_key);
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}
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// Cancel any pending checks on PIO "ack" state machine
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static void
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pio_ack_cancel(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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pio_hw->txf[2] = 0;
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}
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// Test if PIO "rx" state machine has overflowed its fifos
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// Check if the PIO "tx" state machine stopped due to passive/dominant conflict
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static int
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pio_rx_check_stall(struct can2040 *cd)
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pio_tx_did_conflict(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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return pio_hw->fdebug & (1 << (PIO_FDEBUG_RXSTALL_LSB + 1));
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return pio_hw->sm[3].addr == can2040_offset_tx_conflict;
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}
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// Report number of bytes still pending in PIO "rx" fifo queue
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static int
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pio_rx_fifo_level(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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return (pio_hw->flevel & PIO_FLEVEL_RX1_BITS) >> PIO_FLEVEL_RX1_LSB;
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}
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// Enable host irq on a "may start transmit" signal (sm irq 0)
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// Enable host irq on a "may transmit" signal (sm irq 0)
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static void
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pio_irq_set_maytx(struct can2040 *cd)
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{
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@ -286,9 +310,9 @@ pio_irq_set_maytx(struct can2040 *cd)
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pio_hw->inte0 = PIO_IRQ0_INTE_SM0_BITS | PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS;
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}
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// Enable host irq on a "may transmit" or "match tx" signal (sm irq 0 or 2)
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// Enable host irq on a "may transmit" or "matched" signal (sm irq 0 or 2)
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static void
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pio_irq_set_maytx_matchtx(struct can2040 *cd)
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pio_irq_set_maytx_matched(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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pio_hw->inte0 = (PIO_IRQ0_INTE_SM0_BITS | PIO_IRQ0_INTE_SM2_BITS
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@ -304,7 +328,7 @@ pio_irq_set_maytx_ackdone(struct can2040 *cd)
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| PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS);
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}
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// Atomically enable "may start transmit" signal (sm irq 0)
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// Atomically enable "may transmit" signal (sm irq 0)
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static void
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pio_irq_atomic_set_maytx(struct can2040 *cd)
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{
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@ -320,24 +344,6 @@ pio_irq_set_none(struct can2040 *cd)
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pio_hw->inte0 = PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS;
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}
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// Set PIO "sync" machine to signal "start transmit" (sm irq 0) on 11 idle bits
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static void
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pio_sync_normal_start_signal(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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uint32_t eom_idx = can2040_offset_sync_found_end_of_message;
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pio_hw->instr_mem[eom_idx] = 0xe13a; // set x, 26 [1]
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}
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// Set PIO "sync" machine to signal "start transmit" (sm irq 0) on 17 idle bits
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static void
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pio_sync_slow_start_signal(struct can2040 *cd)
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{
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pio_hw_t *pio_hw = cd->pio_hw;
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uint32_t eom_idx = can2040_offset_sync_found_end_of_message;
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pio_hw->instr_mem[eom_idx] = 0xa127; // mov x, osr [1]
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}
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// Setup PIO state machines
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static void
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pio_sm_setup(struct can2040 *cd)
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@ -355,7 +361,7 @@ pio_sm_setup(struct can2040 *cd)
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// Set initial state machine state
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pio_sync_setup(cd);
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pio_rx_setup(cd);
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pio_ack_setup(cd);
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pio_match_setup(cd);
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pio_tx_setup(cd);
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// Start state machines
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@ -658,6 +664,8 @@ report_note_ack_success(struct can2040 *cd)
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static void
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report_note_eof(struct can2040 *cd)
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{
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if (cd->report_state == RS_IDLE)
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return;
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if (cd->report_state & RS_AWAIT_EOF) {
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if (cd->report_state & RS_IS_TX)
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report_tx_msg(cd);
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@ -665,13 +673,17 @@ report_note_eof(struct can2040 *cd)
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report_rx_msg(cd);
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}
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cd->report_state = RS_IDLE;
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pio_match_clear(cd);
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}
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// Parser found unexpected data on input
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static void
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report_note_parse_error(struct can2040 *cd)
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{
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if (cd->report_state == RS_IDLE)
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return;
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cd->report_state = RS_IDLE;
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pio_match_clear(cd);
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}
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// Check if in an rx ack is pending
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@ -706,8 +718,6 @@ tx_schedule_transmit(struct can2040 *cd)
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if (!pio_tx_did_conflict(cd))
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// Already queued or actively transmitting
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return;
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} else if (cd->tx_state != TS_IDLE) {
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pio_ack_cancel(cd);
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}
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if (cd->tx_push_pos == cd->tx_pull_pos) {
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// No new messages to transmit
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@ -733,20 +743,20 @@ tx_note_crc_start(struct can2040 *cd, uint32_t parse_crc)
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uint32_t cs = cd->unstuf.count_stuff;
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uint32_t crcstart_bitpos = cd->raw_bit_count - cs - 1;
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uint32_t last = ((cd->unstuf.stuffed_bits >> cs) << 15) | parse_crc;
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int crc_bitcount = bitstuff(&last, 15 + 1) - 1;
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uint32_t crc_bitcount = bitstuff(&last, 15 + 1) - 1;
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uint32_t crcend_bitpos = crcstart_bitpos + crc_bitcount;
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struct can2040_transmit *qt = &cd->tx_queue[tx_qpos(cd, cd->tx_pull_pos)];
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struct can2040_msg *pm = &cd->parse_msg;
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struct can2040_msg *pm = &cd->parse_msg, *tm = &qt->msg;
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if (cd->tx_state == TS_QUEUED) {
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if (qt->crc == cd->parse_crc
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&& qt->msg.id == pm->id && qt->msg.dlc == pm->dlc
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&& qt->msg.data32[0] == pm->data32[0]
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&& qt->msg.data32[1] == pm->data32[1]) {
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if (qt->crc == parse_crc && tm->id == pm->id && tm->dlc == pm->dlc
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&& tm->data32[0] == pm->data32[0]
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&& tm->data32[1] == pm->data32[1]) {
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// This is a self transmit - setup confirmation signal
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report_note_crc_start(cd, 1);
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cd->tx_state = TS_CONFIRM_TX;
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last = (last << 10) | 0x02ff;
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pio_ack_check(cd, last, crcstart_bitpos + crc_bitcount + 10);
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pio_match_check(cd, pio_match_calc_key(last, crcend_bitpos + 10));
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return;
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}
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if (!pio_tx_did_conflict(cd) && pio_rx_fifo_level(cd) > 1) {
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@ -760,8 +770,10 @@ tx_note_crc_start(struct can2040 *cd, uint32_t parse_crc)
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report_note_crc_start(cd, 0);
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cd->tx_state = TS_ACKING_RX;
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last = (last << 1) | 0x01;
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pio_ack_inject(cd, last, crcstart_bitpos + crc_bitcount + 1);
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pio_tx_inject_ack(cd, pio_match_calc_key(last, crcend_bitpos + 1));
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pio_irq_set_maytx_ackdone(cd);
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last = (last << 8) | 0x7f;
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cd->tx_eof_key = pio_match_calc_key(last, crcend_bitpos + 9);
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}
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// Ack phase succeeded
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@ -770,7 +782,7 @@ tx_note_ack_success(struct can2040 *cd)
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{
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report_note_ack_success(cd);
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if (cd->tx_state == TS_CONFIRM_TX)
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pio_irq_set_maytx_matchtx(cd);
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pio_irq_set_maytx_matched(cd);
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}
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// EOF phase succeeded - report message (rx or tx) to calling code
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@ -794,13 +806,15 @@ tx_note_parse_error(struct can2040 *cd)
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static void
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tx_line_ackdone(struct can2040 *cd)
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{
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pio_irq_set_maytx(cd);
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report_note_ack_success(cd);
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pio_match_check(cd, cd->tx_eof_key);
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pio_irq_set_maytx_matched(cd);
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tx_schedule_transmit(cd);
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}
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// Received PIO "matchtx" irq
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// Received PIO "matched" irq
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static void
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tx_line_matchtx(struct can2040 *cd)
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tx_line_matched(struct can2040 *cd)
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{
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tx_note_eof_success(cd);
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pio_irq_set_none(cd);
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@ -1104,7 +1118,7 @@ can2040_pio_irq_handler(struct can2040 *cd)
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tx_line_ackdone(cd);
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else if (ints & PIO_IRQ0_INTE_SM2_BITS)
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// Transmit message completed successfully
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tx_line_matchtx(cd);
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tx_line_matched(cd);
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else if (ints & PIO_IRQ0_INTE_SM0_BITS)
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// Bus is idle, but not all bits may have been flushed yet
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tx_line_maytx(cd);
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@ -71,6 +71,7 @@ struct can2040 {
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// Transmits
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uint32_t tx_state;
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uint32_t tx_eof_key;
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uint32_t tx_pull_pos, tx_push_pos;
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struct can2040_transmit tx_queue[4];
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};
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