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stm32: 25MHz clock fixes 

Signed-off-by: Arkadiusz Raj <arek.raj@gmail.com>
This commit is contained in:
Arkadiusz Raj 2021-02-19 16:40:10 +00:00 committed by Kevin O'Connor
parent a6e28f7d6a
commit 28e41806f5
1 changed files with 2 additions and 1 deletions
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3
src/stm32/stm32f4.c
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@ -145,7 +145,8 @@ enable_clock_stm32f40x(void)
{
#if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 \
|| CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F429
uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
uint32_t pll_base = (CONFIG_STM32_CLOCK_REF_25M) ? 1000000 : 2000000;
uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 168Mhz PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;