From 267a2f3a38cafd1949a9e276b7020030e9c9c0a4 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Fri, 19 Feb 2021 12:19:32 -0500 Subject: [PATCH] stm32: Optimize stm32f401 peripheral clock Signed-off-by: Kevin O'Connor --- src/stm32/stm32f4.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index dc7a15aa..4bab40bc 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -12,7 +12,8 @@ #include "internal.h" // enable_pclock #include "sched.h" // sched_main -#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4) +#define FREQ_PERIPH_DIV (CONFIG_MACH_STM32F401 ? 2 : 4) +#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV) #define FREQ_USB 48000000 // Enable a peripheral clock @@ -236,7 +237,10 @@ clock_setup(void) ; // Switch system clock to PLL - RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL; + if (FREQ_PERIPH_DIV == 2) + RCC->CFGR = RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_SW_PLL; + else + RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL; while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) ; }