mirror of https://github.com/Desuuuu/klipper.git
stm32: stm32g0b1 fdcan support (#5488)
Signed-off-by: Alan.Ma from BigTreeTech <tech@biqu3d.com>
This commit is contained in:
BIGTREETECH
GitHub
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af38d708cb
commit
1ff7261203
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@ -101,6 +101,9 @@ config HAVE_STM32_USBOTG
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config HAVE_STM32_CANBUS
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bool
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default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
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config HAVE_STM32_FDCANBUS
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bool
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default y if MACH_STM32G0
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config MCU
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string
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@ -275,6 +278,8 @@ config SERIAL
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bool
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config CANSERIAL
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bool
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config FDCANSERIAL
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bool
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choice
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prompt "Communication interface"
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config STM32_USB_PA11_PA12
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@ -342,10 +347,14 @@ choice
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bool "CAN bus (on PD0/PD1)" if LOW_LEVEL_OPTIONS
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depends on HAVE_STM32_CANBUS
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select CANSERIAL
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config STM32_CANBUS_PB0_PB1
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bool "CAN bus (on PB0/PB1)" if LOW_LEVEL_OPTIONS
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depends on HAVE_STM32_FDCANBUS
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select FDCANSERIAL
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endchoice
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config CANBUS_FREQUENCY
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int "CAN bus speed" if LOW_LEVEL_OPTIONS && CANSERIAL
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int "CAN bus speed" if LOW_LEVEL_OPTIONS && (CANSERIAL || FDCANSERIAL)
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default 500000
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endif
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@ -61,9 +61,12 @@ serial-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_serial.c
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src-$(CONFIG_SERIAL) += $(serial-src-y) generic/serial_irq.c
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src-$(CONFIG_CANSERIAL) += stm32/can.c ../lib/fast-hash/fasthash.c
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src-$(CONFIG_CANSERIAL) += generic/canbus.c
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src-$(CONFIG_FDCANSERIAL) += stm32/fdcan.c ../lib/fast-hash/fasthash.c
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src-$(CONFIG_FDCANSERIAL) += generic/canbus.c
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src-$(CONFIG_HAVE_GPIO_HARD_PWM) += stm32/hard_pwm.c
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dirs-$(CONFIG_CANSERIAL) += lib/fast-hash
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dirs-$(CONFIG_FDCANSERIAL) += lib/fast-hash
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# Binary output file rules
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target-y += $(OUT)klipper.bin
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@ -252,7 +252,7 @@ compute_btr(uint32_t pclock, uint32_t bitrate)
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uint32_t bit_clocks = pclock / bitrate; // clock ticks per bit
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uint32_t sjw = 2;
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uint32_t sjw = 2;
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uint32_t qs;
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// Find number of time quantas that gives us the exact wanted bit time
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for (qs = 18; qs > 9; qs--) {
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@ -0,0 +1,331 @@
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// Serial over CAN emulation for STM32 boards.
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//
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// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
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// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
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// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // memcpy
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#include "autoconf.h" // CONFIG_MACH_STM32F1
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#include "board/irq.h" // irq_disable
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#include "command.h" // DECL_CONSTANT_STR
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#include "fasthash.h" // fasthash64
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#include "generic/armcm_boot.h" // armcm_enable_irq
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#include "generic/canbus.h" // canbus_notify_tx
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#include "generic/serial_irq.h" // serial_rx_byte
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#include "internal.h" // enable_pclock
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#include "sched.h" // DECL_INIT
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/*
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FDCAN max date length = 64bytes
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data_len[] is the data length & DLC mapping table
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Required when the data length exceeds 64bytes
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*/
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uint8_t data_len[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
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typedef struct
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{
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uint32_t RESERVED0 : 18;
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__IO uint32_t ID : 11;
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__IO uint32_t RTR : 1;
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__IO uint32_t XTD : 1;
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__IO uint32_t ESI : 1;
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__IO uint32_t RXTS : 16;
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__IO uint32_t DLC : 4;
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__IO uint32_t BRS : 1;
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__IO uint32_t FDF : 1;
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uint32_t RESERVED1 : 2;
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__IO uint32_t FIDX : 7;
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__IO uint32_t ANMF : 1;
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__IO uint8_t data[64];
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}FDCAN_RX_FIFO_TypeDef;
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typedef struct
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{
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__IO uint32_t id_section;
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__IO uint32_t dlc_section;
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__IO uint32_t data[64 / 4];
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}FDCAN_TX_FIFO_TypeDef;
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typedef struct
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{
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__IO uint32_t FLS[28]; // Filter list standard
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__IO uint32_t FLE[16]; // Filter list extended
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FDCAN_RX_FIFO_TypeDef RXF0[3];
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FDCAN_RX_FIFO_TypeDef RXF1[3];
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__IO uint32_t TEF[6]; // Tx event FIFO
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FDCAN_TX_FIFO_TypeDef TXFIFO[3];
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}FDCAN_MSG_RAM_TypeDef;
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typedef struct
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{
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FDCAN_MSG_RAM_TypeDef fdcan1;
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FDCAN_MSG_RAM_TypeDef fdcan2;
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}FDCAN_RAM_TypeDef;
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FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
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#define FDCAN_IE_RX_FIFO0 (FDCAN_IE_RF0NE | FDCAN_IE_RF0FE | FDCAN_IE_RF0LE)
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#define FDCAN_IE_RX_FIFO1 (FDCAN_IE_RF1NE | FDCAN_IE_RF1FE | FDCAN_IE_RF1LE)
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#define FDCAN_IE_TC (FDCAN_IE_TCE | FDCAN_IE_TCFE | FDCAN_IE_TFEE)
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#if CONFIG_STM32_CANBUS_PB0_PB1
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1");
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#define GPIO_Rx GPIO('B', 0)
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#define GPIO_Tx GPIO('B', 1)
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#endif
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#if CONFIG_MACH_STM32G0
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#if CONFIG_STM32_CANBUS_PB0_PB1
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#define SOC_CAN FDCAN2
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#define MSG_RAM fdcan_ram->fdcan2
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#else
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#error Uknown pins for STMF32G0 CAN
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#endif
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#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
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#define CAN_IT1_IRQn TIM17_FDCAN_IT1_IRQn
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#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
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#endif
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#ifndef SOC_CAN
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#error No known CAN device for configured MCU
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#endif
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// Read the next CAN packet
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int
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canbus_read(uint32_t *id, uint8_t *data)
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{
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if (!(SOC_CAN->RXF0S & FDCAN_RXF0S_F0FL)) {
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// All rx mboxes empty, enable wake on rx IRQ
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irq_disable();
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SOC_CAN->IE |= FDCAN_IE_RF0NE;
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irq_enable();
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return -1;
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}
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// Read and ack packet
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uint32_t r_index = ((SOC_CAN->RXF0S & FDCAN_RXF0S_F0GI)
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>> FDCAN_RXF0S_F0GI_Pos);
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FDCAN_RX_FIFO_TypeDef *rxf0 = &MSG_RAM.RXF0[r_index];
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uint32_t dlc = rxf0->DLC;
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*id = rxf0->ID;
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for (uint8_t i = 0; i < dlc; i++) {
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data[i] = rxf0->data[i];
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}
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SOC_CAN->RXF0A = r_index;
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return dlc;
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}
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// Transmit a packet
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int
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canbus_send(uint32_t id, uint32_t len, uint8_t *data)
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{
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uint32_t txfqs = SOC_CAN->TXFQS;
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if (txfqs & FDCAN_TXFQS_TFQF) {
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// No space in transmit fifo - enable tx irq
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irq_disable();
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SOC_CAN->IE |= FDCAN_IE_TC;
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irq_enable();
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return -1;
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}
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uint32_t w_index = ((txfqs & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
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FDCAN_TX_FIFO_TypeDef *txfifo = &MSG_RAM.TXFIFO[w_index];
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txfifo->id_section = id << 18;
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txfifo->dlc_section = len << 16;
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if (len) {
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txfifo->data[0] = (((uint32_t)data[3] << 24)
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| ((uint32_t)data[2] << 16)
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| ((uint32_t)data[1] << 8)
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| ((uint32_t)data[0] << 0));
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txfifo->data[1] = (((uint32_t)data[7] << 24)
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| ((uint32_t)data[6] << 16)
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| ((uint32_t)data[5] << 8)
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| ((uint32_t)data[4] << 0));
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}
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SOC_CAN->TXBAR = ((uint32_t)1 << w_index);
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return len;
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}
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void can_filter(uint32_t id, uint8_t index)
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{
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MSG_RAM.FLS[index] = ((0x2 << 30) // Classic filter
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| (0x1 << 27) // Store in Rx FIFO 0 if filter matches
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| (id << 16)
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| 0x7FF); // mask all enabled
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}
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// Setup the receive packet filter
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void
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canbus_set_filter(uint32_t id)
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{
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/* Request initialisation */
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SOC_CAN->CCCR |= FDCAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(SOC_CAN->CCCR & FDCAN_CCCR_INIT))
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;
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/* Enable configuration change */
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SOC_CAN->CCCR |= FDCAN_CCCR_CCE;
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can_filter(CANBUS_ID_ADMIN, 0);
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/* List size standard */
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SOC_CAN->RXGFC &= ~(FDCAN_RXGFC_LSS);
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SOC_CAN->RXGFC |= 1 << FDCAN_RXGFC_LSS_Pos;
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/* Filter remote frames with 11-bit standard IDs
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Non-matching frames standard reject or accept in Rx FIFO 1 */
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SOC_CAN->RXGFC &= ~(FDCAN_RXGFC_RRFS | FDCAN_RXGFC_ANFS);
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SOC_CAN->RXGFC |= ((0 << FDCAN_RXGFC_RRFS_Pos)
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| ((id ? 0x01 : 0x02) << FDCAN_RXGFC_ANFS_Pos));
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/* Leave the initialisation mode for the filter */
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT;
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}
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// This function handles CAN global interrupts
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void
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CAN_IRQHandler(void)
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{
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uint32_t ir = SOC_CAN->IR;
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uint32_t ie = SOC_CAN->IE;
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if (ir & FDCAN_IE_RX_FIFO1 && ie & FDCAN_IE_RX_FIFO1) {
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SOC_CAN->IR = FDCAN_IE_RX_FIFO1;
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if (SOC_CAN->RXF1S & FDCAN_RXF1S_F1FL) {
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// Read and ack data packet
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uint32_t r_index = ((SOC_CAN->RXF1S & FDCAN_RXF1S_F1GI)
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>> FDCAN_RXF1S_F1GI_Pos);
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FDCAN_RX_FIFO_TypeDef *rxf1 = &MSG_RAM.RXF1[r_index];
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uint32_t rir_id = rxf1->ID;
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uint32_t dlc = rxf1->DLC;
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uint8_t data[8];
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for (uint8_t i = 0; i < dlc; i++) {
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data[i] = rxf1->data[i];
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}
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SOC_CAN->RXF1A = r_index;
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// Process packet
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canbus_process_data(rir_id, dlc, data);
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}
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}
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if (ie & FDCAN_IE_RX_FIFO0 && ir & FDCAN_IE_RX_FIFO0) {
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// Admin Rx
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SOC_CAN->IR = FDCAN_IE_RX_FIFO0;
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canbus_notify_rx();
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}
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if (ie & FDCAN_IE_TC && ir & FDCAN_IE_TC) {
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// Tx
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SOC_CAN->IR = FDCAN_IE_TC;
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canbus_notify_tx();
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}
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}
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static inline const uint32_t
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make_btr(uint32_t sjw, // Sync jump width, ... hmm
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uint32_t time_seg1, // time segment before sample point, 1 .. 16
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uint32_t time_seg2, // time segment after sample point, 1 .. 8
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uint32_t brp) // Baud rate prescaler, 1 .. 1024
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{
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return (((uint32_t)(sjw-1)) << FDCAN_NBTP_NSJW_Pos
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| ((uint32_t)(time_seg1-1)) << FDCAN_NBTP_NTSEG1_Pos
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| ((uint32_t)(time_seg2-1)) << FDCAN_NBTP_NTSEG2_Pos
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| ((uint32_t)(brp - 1)) << FDCAN_NBTP_NBRP_Pos);
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}
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static inline const uint32_t
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compute_btr(uint32_t pclock, uint32_t bitrate)
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{
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/*
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Some equations:
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Tpclock = 1 / pclock
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Tq = brp * Tpclock
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Tbs1 = Tq * TS1
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Tbs2 = Tq * TS2
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NominalBitTime = Tq + Tbs1 + Tbs2
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BaudRate = 1/NominalBitTime
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Bit value sample point is after Tq+Tbs1. Ideal sample point
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is at 87.5% of NominalBitTime
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Use the lowest brp where ts1 and ts2 are in valid range
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*/
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uint32_t bit_clocks = pclock / bitrate; // clock ticks per bit
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uint32_t sjw = 2;
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uint32_t qs;
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// Find number of time quantas that gives us the exact wanted bit time
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for (qs = 18; qs > 9; qs--) {
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// check that bit_clocks / quantas is an integer
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uint32_t brp_rem = bit_clocks % qs;
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if (brp_rem == 0)
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break;
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}
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uint32_t brp = bit_clocks / qs;
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uint32_t time_seg2 = qs / 8; // sample at ~87.5%
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uint32_t time_seg1 = qs - (1 + time_seg2);
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return make_btr(sjw, time_seg1, time_seg2, brp);
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}
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void
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can_init(void)
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{
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enable_pclock((uint32_t)SOC_CAN);
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gpio_peripheral(GPIO_Rx, CAN_FUNCTION, 1);
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gpio_peripheral(GPIO_Tx, CAN_FUNCTION, 0);
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uint32_t pclock = get_pclock_frequency((uint32_t)SOC_CAN);
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uint32_t btr = compute_btr(pclock, CONFIG_CANBUS_FREQUENCY);
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/*##-1- Configure the CAN #######################################*/
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/* Exit from sleep mode */
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CSR;
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/* Wait the acknowledge */
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while (SOC_CAN->CCCR & FDCAN_CCCR_CSA)
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;
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/* Request initialisation */
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SOC_CAN->CCCR |= FDCAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(SOC_CAN->CCCR & FDCAN_CCCR_INIT))
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;
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/* Enable configuration change */
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SOC_CAN->CCCR |= FDCAN_CCCR_CCE;
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if (SOC_CAN == FDCAN1)
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FDCAN_CONFIG->CKDIV = 0;
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/* Disable automatic retransmission */
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SOC_CAN->CCCR |= FDCAN_CCCR_DAR;
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/* Disable protocol exception handling */
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SOC_CAN->CCCR |= FDCAN_CCCR_PXHD;
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SOC_CAN->NBTP = btr;
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/* Leave the initialisation mode */
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SOC_CAN->CCCR &= ~FDCAN_CCCR_CCE;
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SOC_CAN->CCCR &= ~FDCAN_CCCR_INIT;
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/*##-2- Configure the CAN Filter #######################################*/
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canbus_set_filter(0);
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/*##-3- Configure Interrupts #################################*/
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armcm_enable_irq(CAN_IRQHandler, CAN_IT0_IRQn, 0);
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if (CAN_IT0_IRQn != CAN_IT1_IRQn)
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armcm_enable_irq(CAN_IRQHandler, CAN_IT1_IRQn, 0);
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SOC_CAN->ILE |= 0x03;
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SOC_CAN->IE |= FDCAN_IE_RX_FIFO0 | FDCAN_IE_RX_FIFO1;
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// Convert unique 96-bit chip id into 48 bit representation
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uint64_t hash = fasthash64((uint8_t*)UID_BASE, 12, 0xA16231A7);
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canbus_set_uuid(&hash);
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}
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DECL_INIT(can_init);
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@ -30,6 +30,8 @@ lookup_clock_line(uint32_t periph_base)
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uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit};
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}
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if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE))
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12};
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if (periph_base == USB_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13};
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if (periph_base == CRS_BASE)
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