diff --git a/src/atsam/Kconfig b/src/atsam/Kconfig
index 2ac185ac..48ec8eec 100644
--- a/src/atsam/Kconfig
+++ b/src/atsam/Kconfig
@@ -9,6 +9,7 @@ config ATSAM_SELECT
     select HAVE_GPIO_ADC
     select HAVE_GPIO_I2C
     select HAVE_GPIO_SPI
+    select HAVE_GPIO_HARD_PWM
     select HAVE_GPIO_BITBANGING
 
 config BOARD_DIRECTORY
diff --git a/src/atsam/Makefile b/src/atsam/Makefile
index 18c25006..781b204e 100644
--- a/src/atsam/Makefile
+++ b/src/atsam/Makefile
@@ -29,7 +29,7 @@ eflags-$(CONFIG_MACH_SAM4E) += -T lib/sam4e/gcc/gcc/sam4e8e_flash.ld
 CFLAGS_klipper.elf += $(eflags-y) --specs=nano.specs --specs=nosys.specs
 
 # Add source files
-src-y += atsam/main.c atsam/gpio.c atsam/i2c.c atsam/spi.c
+src-y += atsam/main.c atsam/gpio.c atsam/i2c.c atsam/spi.c atsam/hard_pwm.c
 src-y += generic/crc16_ccitt.c generic/alloc.c
 src-y += generic/armcm_irq.c generic/armcm_timer.c
 usbserial-$(CONFIG_MACH_SAM3X) := atsam/sam3_usb.c
diff --git a/src/atsam/gpio.h b/src/atsam/gpio.h
index e106e094..5b5c8139 100644
--- a/src/atsam/gpio.h
+++ b/src/atsam/gpio.h
@@ -1,5 +1,5 @@
-#ifndef __SAM3_GPIO_H
-#define __SAM3_GPIO_H
+#ifndef __ATSAM_GPIO_H
+#define __ATSAM_GPIO_H
 
 #include <stdint.h> // uint32_t
 
@@ -21,6 +21,12 @@ struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up);
 void gpio_in_reset(struct gpio_in g, int8_t pull_up);
 uint8_t gpio_in_read(struct gpio_in g);
 
+struct gpio_pwm {
+    void *reg;
+};
+struct gpio_pwm gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val);
+void gpio_pwm_write(struct gpio_pwm g, uint8_t val);
+
 struct gpio_adc {
     uint32_t chan;
 };
diff --git a/src/atsam/hard_pwm.c b/src/atsam/hard_pwm.c
new file mode 100644
index 00000000..8bfd6305
--- /dev/null
+++ b/src/atsam/hard_pwm.c
@@ -0,0 +1,96 @@
+// Hardware PWM support on atsam
+//
+// Copyright (C) 2019  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "command.h" // shutdown
+#include "gpio.h" // gpio_pwm_write
+#include "internal.h" // GPIO
+#include "sched.h" // sched_shutdown
+
+struct gpio_pwm_info {
+    uint8_t gpio, channel, ptype;
+};
+
+static const struct gpio_pwm_info pwm_regs[] = {
+#if CONFIG_MACH_SAM3X
+    { GPIO('A', 21), 0, 'B' },
+    { GPIO('B', 16), 0, 'B' },
+    { GPIO('A', 12), 1, 'B' },
+    { GPIO('B', 17), 1, 'B' },
+    { GPIO('A', 20), 2, 'B' },
+    { GPIO('B', 18), 2, 'B' },
+    { GPIO('A', 0),  3, 'B' },
+    { GPIO('B', 19), 3, 'B' },
+#if CONFIG_MACH_SAM3X8E
+    { GPIO('C', 2),  0, 'B' },
+    { GPIO('C', 4),  1, 'B' },
+    { GPIO('C', 6),  2, 'B' },
+    { GPIO('C', 8),  3, 'B' },
+    { GPIO('C', 21), 4, 'B' },
+    { GPIO('C', 22), 5, 'B' },
+    { GPIO('C', 23), 6, 'B' },
+    { GPIO('C', 24), 7, 'B' },
+#endif
+#elif CONFIG_MACH_SAM4
+    { GPIO('A', 19), 0, 'B' },
+    { GPIO('B', 5),  0, 'B' },
+    { GPIO('C', 0),  0, 'B' },
+    { GPIO('C', 13), 0, 'B' },
+    { GPIO('A', 20), 1, 'B' },
+    { GPIO('B', 12), 1, 'A' },
+    { GPIO('C', 1),  1, 'B' },
+    { GPIO('C', 15), 1, 'B' },
+    { GPIO('A', 16), 2, 'C' },
+    { GPIO('A', 30), 2, 'A' },
+    { GPIO('B', 13), 2, 'A' },
+    { GPIO('C', 2),  2, 'B' },
+    { GPIO('A', 15), 3, 'C' },
+    { GPIO('C', 3),  3, 'B' },
+    { GPIO('C', 22), 3, 'B' },
+#endif
+};
+
+#define MAX_PWM 255
+
+DECL_CONSTANT(PWM_MAX, MAX_PWM);
+
+struct gpio_pwm
+gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
+{
+    // Find pin in pwm_regs table
+    const struct gpio_pwm_info *p = pwm_regs;
+    for (; ; p++) {
+        if (p >= &pwm_regs[ARRAY_SIZE(pwm_regs)])
+            shutdown("Not a valid PWM pin");
+        if (p->gpio == pin)
+            break;
+    }
+
+    // Map cycle_time to pwm clock divisor
+    uint32_t div;
+    for (div=0; div<10; div++)
+        if (cycle_time < (MAX_PWM << div) / 2)
+            break;
+
+    // Enable clock
+    enable_pclock(ID_PWM);
+
+    // Enable PWM output
+    if (PWM->PWM_SR & (1 << p->channel))
+        shutdown("PWM channel already in use");
+    gpio_peripheral(pin, p->ptype, 0);
+    PWM->PWM_CH_NUM[p->channel].PWM_CMR = div;
+    PWM->PWM_CH_NUM[p->channel].PWM_CPRD = MAX_PWM;
+    PWM->PWM_CH_NUM[p->channel].PWM_CDTY = val;
+    PWM->PWM_ENA = 1 << p->channel;
+
+    return (struct gpio_pwm){ (void*)&PWM->PWM_CH_NUM[p->channel].PWM_CDTYUPD };
+}
+
+void
+gpio_pwm_write(struct gpio_pwm g, uint8_t val)
+{
+    *(volatile uint32_t*)g.reg = val;
+}