mirror of https://github.com/Desuuuu/klipper.git
rp2040: Add initial support for the rp2040 mcu
Support the rp2040 (as tested on a Raspberry Pi Pico board). This adds basic uart, timer, gpio, and watchdog support. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
20c5976356
commit
045bfa4e8d
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@ -21,6 +21,8 @@ choice
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bool "LPC176x (Smoothieboard)"
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config MACH_STM32
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bool "STMicroelectronics STM32"
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config MACH_RP2040
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bool "Raspberry Pi RP2040"
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config MACH_PRU
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bool "Beaglebone PRU"
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config MACH_LINUX
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@ -34,6 +36,7 @@ source "src/atsam/Kconfig"
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source "src/atsamd/Kconfig"
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source "src/lpc176x/Kconfig"
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source "src/stm32/Kconfig"
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source "src/rp2040/Kconfig"
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source "src/pru/Kconfig"
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source "src/linux/Kconfig"
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source "src/simulator/Kconfig"
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@ -0,0 +1,59 @@
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# Kconfig settings for STM32 processors
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if MACH_RP2040
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config RP2040_SELECT
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bool
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default y
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select HAVE_GPIO
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select HAVE_GPIO_BITBANGING
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select HAVE_STRICT_TIMING
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config BOARD_DIRECTORY
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string
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default "rp2040"
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config MCU
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string
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default "rp2040"
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config CLOCK_FREQ
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int
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default 12000000
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config FLASH_SIZE
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hex
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default 0x200000
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config RAM_START
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hex
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default 0x20000000
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config RAM_SIZE
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hex
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default 0x42000
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config STACK_SIZE
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int
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default 512
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config FLASH_START
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hex
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default 0x10000000
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######################################################################
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# Communication inteface
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######################################################################
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config USBSERIAL
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bool
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config SERIAL
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bool
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choice
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prompt "Communication interface"
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config RP2040_SERIAL_UART0
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bool "Serial (on UART0 GPIO1/GPIO0)"
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select SERIAL
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endchoice
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endif
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@ -0,0 +1,48 @@
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# Additional RP2040 build rules
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# Setup the toolchain
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/rp2040 src/generic lib/rp2040/elf2uf2
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CFLAGS += -mcpu=cortex-m0plus -mthumb -Ilib/cmsis-core
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CFLAGS += -Ilib/rp2040 -Ilib/rp2040/cmsis_include
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CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
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CFLAGS_klipper.elf += -T $(OUT)src/rp2040/rp2040_link.ld
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$(OUT)klipper.elf: $(OUT)stage2.o $(OUT)src/rp2040/rp2040_link.ld
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# Add source files
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src-y += rp2040/main.c rp2040/gpio.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-y += generic/timer_irq.c rp2040/timer.c
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src-$(CONFIG_SERIAL) += rp2040/serial.c generic/serial_irq.c
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# rp2040 stage2 building
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$(OUT)stage2.o: lib/rp2040/boot_stage2/boot2_w25q080.S
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@echo " Building rp2040 stage2 $@"
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$(Q)$(CC) $(CFLAGS) -Ilib/rp2040/boot_stage2 -Ilib/rp2040/boot_stage2/asminclude -DPICO_FLASH_SPI_CLKDIV=2 -c $< -o $(OUT)stage2raw1.o
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$(Q)$(LD) $(OUT)stage2raw1.o -nostartfiles --script=lib/rp2040/boot_stage2/boot_stage2.ld -o $(OUT)stage2raw.o
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$(Q)$(OBJCOPY) -O binary $(OUT)stage2raw.o $(OUT)stage2raw.bin
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$(Q)lib/rp2040/boot_stage2/pad_checksum -s 0xffffffff $(OUT)stage2raw.bin $(OUT)stage2.S
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$(Q)$(CC) $(CFLAGS) -c $(OUT)stage2.S -o $(OUT)stage2.o
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OBJS_klipper.elf += $(OUT)stage2.o
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# Binary output file rules
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target-y += $(OUT)klipper.uf2
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$(OUT)lib/rp2040/elf2uf2/elf2uf2: lib/rp2040/elf2uf2/main.cpp
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@echo " Building $@"
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$(Q)g++ -g -O -Ilib/rp2040 $< -o $@
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$(OUT)klipper.uf2: $(OUT)klipper.elf $(OUT)lib/rp2040/elf2uf2/elf2uf2
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@echo " Creating uf2 file $@"
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$(Q)$(OUT)lib/rp2040/elf2uf2/elf2uf2 $< $@
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# Flash rules
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flash: $(OUT)klipper.uf2
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@echo "Error: Flashing not supported on rp2040."
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@echo "Place target board in bootloader mode (hold bootsel button"
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@echo "during powerup), mount the device as a usb drive, and copy"
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@echo "$< to the device."
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@exit -1
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@ -0,0 +1,119 @@
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// GPIO functions on rp2040
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//
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// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // ffs
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#include "board/irq.h" // irq_save
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#include "command.h" // shutdown
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#include "gpio.h" // gpio_out_setup
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#include "hardware/structs/iobank0.h" // iobank0_hw
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#include "hardware/structs/padsbank0.h" // padsbank0_hw
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#include "hardware/structs/sio.h" // sio_hw
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#include "internal.h" // gpio_peripheral
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#include "sched.h" // sched_shutdown
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/****************************************************************
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* Pin mappings
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****************************************************************/
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DECL_ENUMERATION_RANGE("pin", "gpio0", 0, 30);
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, int func, int pull_up)
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{
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padsbank0_hw->io[gpio] = (
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PADS_BANK0_GPIO0_IE_BITS
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| (PADS_BANK0_GPIO0_DRIVE_VALUE_4MA << PADS_BANK0_GPIO0_DRIVE_MSB)
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| (pull_up > 0 ? PADS_BANK0_GPIO0_PUE_BITS : 0)
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| (pull_up < 0 ? PADS_BANK0_GPIO0_PDE_BITS : 0));
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iobank0_hw->io[gpio].ctrl = func << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
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}
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// Convert a register and bit location back to an integer pin identifier
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static int
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mask_to_pin(uint32_t mask)
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{
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return ffs(mask)-1;
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}
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/****************************************************************
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* General Purpose Input Output (GPIO) pins
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****************************************************************/
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struct gpio_out
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gpio_out_setup(uint8_t pin, uint8_t val)
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{
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if (pin > 30)
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goto fail;
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struct gpio_out g = { .bit=1<<pin };
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gpio_out_reset(g, val);
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return g;
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fail:
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shutdown("Not an output pin");
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}
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void
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gpio_out_reset(struct gpio_out g, uint8_t val)
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{
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int pin = mask_to_pin(g.bit);
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irqstatus_t flag = irq_save();
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gpio_out_write(g, val);
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sio_hw->gpio_oe_set = g.bit;
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gpio_peripheral(pin, 5, 0);
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irq_restore(flag);
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}
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void
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gpio_out_toggle_noirq(struct gpio_out g)
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{
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sio_hw->gpio_togl = g.bit;
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}
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void
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gpio_out_toggle(struct gpio_out g)
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{
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gpio_out_toggle_noirq(g);
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}
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void
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gpio_out_write(struct gpio_out g, uint8_t val)
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{
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if (val)
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sio_hw->gpio_set = g.bit;
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else
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sio_hw->gpio_clr = g.bit;
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}
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struct gpio_in
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gpio_in_setup(uint8_t pin, int8_t pull_up)
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{
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if (pin > 30)
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goto fail;
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struct gpio_in g = { .bit=1<<pin };
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gpio_in_reset(g, pull_up);
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return g;
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fail:
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shutdown("Not an input pin");
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}
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void
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gpio_in_reset(struct gpio_in g, int8_t pull_up)
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{
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int pin = mask_to_pin(g.bit);
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irqstatus_t flag = irq_save();
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gpio_peripheral(pin, 5, pull_up);
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sio_hw->gpio_oe_clr = g.bit;
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irq_restore(flag);
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}
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uint8_t
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gpio_in_read(struct gpio_in g)
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{
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return !!(sio_hw->gpio_in & g.bit);
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}
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@ -0,0 +1,22 @@
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#ifndef __RP2040_GPIO_H
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#define __RP2040_GPIO_H
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#include <stdint.h> // uint32_t
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struct gpio_out {
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uint32_t bit;
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};
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struct gpio_out gpio_out_setup(uint8_t pin, uint8_t val);
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void gpio_out_reset(struct gpio_out g, uint8_t val);
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void gpio_out_toggle_noirq(struct gpio_out g);
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void gpio_out_toggle(struct gpio_out g);
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void gpio_out_write(struct gpio_out g, uint8_t val);
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struct gpio_in {
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uint32_t bit;
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};
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struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up);
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void gpio_in_reset(struct gpio_in g, int8_t pull_up);
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uint8_t gpio_in_read(struct gpio_in g);
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#endif // gpio.h
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@ -0,0 +1,12 @@
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#ifndef __RP2040_INTERNAL_H
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#define __RP2040_INTERNAL_H
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// Local definitions for rp2040
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#include "RP2040.h"
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void enable_pclock(uint32_t reset_bit);
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int is_enabled_pclock(uint32_t reset_bit);
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uint32_t get_pclock_frequency(uint32_t reset_bit);
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void gpio_peripheral(uint32_t gpio, int func, int pull_up);
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#endif // internal.h
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@ -0,0 +1,149 @@
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// Startup code on rp2040
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//
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// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <stdint.h> // uint32_t
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#include "hardware/structs/clocks.h" // clock_hw_t
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#include "hardware/structs/pll.h" // pll_hw_t
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#include "hardware/structs/resets.h" // sio_hw
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#include "hardware/structs/watchdog.h" // watchdog_hw
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#include "hardware/structs/xosc.h" // xosc_hw
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#include "sched.h" // sched_main
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/****************************************************************
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* watchdog handler
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****************************************************************/
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void
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watchdog_reset(void)
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{
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watchdog_hw->load = 0x800000; // ~350ms
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}
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DECL_TASK(watchdog_reset);
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void
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watchdog_init(void)
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{
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watchdog_reset();
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watchdog_hw->ctrl = (WATCHDOG_CTRL_PAUSE_DBG0_BITS
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| WATCHDOG_CTRL_PAUSE_DBG1_BITS
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| WATCHDOG_CTRL_PAUSE_JTAG_BITS
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| WATCHDOG_CTRL_ENABLE_BITS);
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}
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DECL_INIT(watchdog_init);
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/****************************************************************
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* Clock setup
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****************************************************************/
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#define FREQ_XOSC 12000000
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#define FREQ_SYS 125000000
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void
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enable_pclock(uint32_t reset_bit)
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{
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resets_hw->reset |= reset_bit;
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resets_hw->reset &= ~reset_bit;
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while (!(resets_hw->reset_done & reset_bit))
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;
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}
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int
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is_enabled_pclock(uint32_t reset_bit)
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{
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return !(resets_hw->reset & reset_bit);
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}
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uint32_t
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get_pclock_frequency(uint32_t reset_bit)
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{
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return FREQ_SYS;
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}
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static void
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xosc_setup(void)
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{
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xosc_hw->startup = DIV_ROUND_UP(FREQ_XOSC, 1000 * 256); // 1ms
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xosc_hw->ctrl = (XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ
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| (XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB));
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while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS))
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;
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}
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static void
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pll_setup(pll_hw_t *pll, uint32_t mul, uint32_t postdiv)
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{
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// Setup pll
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uint32_t refdiv = 1, fbdiv = mul, postdiv2 = 2, postdiv1 = postdiv/postdiv2;
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pll->cs = refdiv;
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pll->fbdiv_int = fbdiv;
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pll->pwr = PLL_PWR_DSMPD_BITS | PLL_PWR_POSTDIVPD_BITS;
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while (!(pll->cs & PLL_CS_LOCK_BITS))
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;
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// Setup post divider
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pll->prim = ((postdiv1 << PLL_PRIM_POSTDIV1_LSB)
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| (postdiv2 << PLL_PRIM_POSTDIV2_LSB));
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pll->pwr = PLL_PWR_DSMPD_BITS;
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}
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static void
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clk_aux_setup(uint32_t clk_id, uint32_t aux_id)
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{
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clock_hw_t *clk = &clocks_hw->clk[clk_id];
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clk->ctrl = 0;
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clk->ctrl = aux_id | CLOCKS_CLK_PERI_CTRL_ENABLE_BITS;
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}
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static void
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clock_setup(void)
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{
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// Set clk_sys and clk_ref to use internal clock
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clock_hw_t *csys = &clocks_hw->clk[clk_sys];
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csys->ctrl &= ~CLOCKS_CLK_SYS_CTRL_SRC_BITS;
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while (csys->selected != 0x1)
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;
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clock_hw_t *cref = &clocks_hw->clk[clk_ref];
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cref->ctrl &= ~CLOCKS_CLK_REF_CTRL_SRC_BITS;
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while (cref->selected != 0x1)
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;
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// Reset peripherals (that can be)
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resets_hw->reset = ~(RESETS_RESET_IO_QSPI_BITS
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| RESETS_RESET_PADS_QSPI_BITS);
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// Setup xosc, pll_sys, and switch clk_sys
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xosc_setup();
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enable_pclock(RESETS_RESET_PLL_SYS_BITS);
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pll_setup(pll_sys_hw, 125, 125*FREQ_XOSC/FREQ_SYS);
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csys->ctrl = 0;
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csys->div = 1<<CLOCKS_CLK_SYS_DIV_INT_LSB;
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csys->ctrl = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX;
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while (!(csys->selected & (1 << 1)))
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;
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// Setup clk_peri
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clk_aux_setup(clk_peri, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS);
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// Enable watchdog tick (at 12Mhz)
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cref->div = 1<<CLOCKS_CLK_REF_DIV_INT_LSB;
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cref->ctrl = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC;
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while (!(cref->selected & (1 << 2)))
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;
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watchdog_hw->tick = 1 | WATCHDOG_TICK_ENABLE_BITS;
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// Enable GPIO control
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enable_pclock(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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clock_setup();
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sched_main();
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}
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|
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@ -0,0 +1,66 @@
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// rp2040 linker script (based on armcm_link.lds.S and customized for stage2)
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//
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// Copyright (C) 2019-2021 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_FLASH_START
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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MEMORY
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{
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rom (rx) : ORIGIN = CONFIG_FLASH_START , LENGTH = CONFIG_FLASH_SIZE
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ram (rwx) : ORIGIN = CONFIG_RAM_START , LENGTH = CONFIG_RAM_SIZE
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}
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SECTIONS
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{
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.text : {
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. = ALIGN(4);
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KEEP(*(.boot2))
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_text_vectortable_start = .;
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KEEP(*(.vector_table))
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_text_vectortable_end = .;
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*(.text .text.*)
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*(.rodata .rodata*)
|
||||
} > rom
|
||||
|
||||
. = ALIGN(4);
|
||||
_data_flash = .;
|
||||
|
||||
.data : AT (_data_flash)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_data_start = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_data_end = .;
|
||||
} > ram
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_bss_start = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_bss_end = .;
|
||||
} > ram
|
||||
|
||||
_stack_start = CONFIG_RAM_START + CONFIG_RAM_SIZE - CONFIG_STACK_SIZE ;
|
||||
.stack _stack_start (NOLOAD) :
|
||||
{
|
||||
. = . + CONFIG_STACK_SIZE;
|
||||
_stack_end = .;
|
||||
} > ram
|
||||
|
||||
/DISCARD/ : {
|
||||
// The .init/.fini sections are used by __libc_init_array(), but
|
||||
// that isn't needed so no need to include them in the binary.
|
||||
*(.init)
|
||||
*(.fini)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
// rp2040 serial
|
||||
//
|
||||
// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
|
||||
//
|
||||
// This file may be distributed under the terms of the GNU GPLv3 license.
|
||||
|
||||
#include <stdint.h> // uint32_t
|
||||
#include "autoconf.h" // CONFIG_SERIAL
|
||||
#include "board/armcm_boot.h" // armcm_enable_irq
|
||||
#include "board/irq.h" // irq_save
|
||||
#include "board/serial_irq.h" // serial_rx_data
|
||||
#include "hardware/structs/resets.h" // RESETS_RESET_UART0_BITS
|
||||
#include "hardware/structs/uart.h" // UART0_BASE
|
||||
#include "internal.h" // UART0_IRQn
|
||||
#include "sched.h" // DECL_INIT
|
||||
|
||||
#define UARTx uart0_hw
|
||||
#define UARTx_IRQn UART0_IRQ_IRQn
|
||||
#define GPIO_Rx 1
|
||||
#define GPIO_Tx 0
|
||||
|
||||
// Write tx bytes to the serial port
|
||||
static void
|
||||
kick_tx(void)
|
||||
{
|
||||
for (;;) {
|
||||
if (UARTx->fr & UART_UARTFR_TXFF_BITS) {
|
||||
// Output fifo full - enable tx irq
|
||||
UARTx->imsc = (UART_UARTIMSC_RXIM_BITS | UART_UARTIMSC_RTIM_BITS
|
||||
| UART_UARTIMSC_TXIM_BITS);
|
||||
break;
|
||||
}
|
||||
uint8_t data;
|
||||
int ret = serial_get_tx_byte(&data);
|
||||
if (ret) {
|
||||
// No more data to send - disable tx irq
|
||||
UARTx->imsc = UART_UARTIMSC_RXIM_BITS | UART_UARTIMSC_RTIM_BITS;
|
||||
break;
|
||||
}
|
||||
UARTx->dr = data;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
UARTx_IRQHandler(void)
|
||||
{
|
||||
uint32_t mis = UARTx->mis;
|
||||
if (mis & (UART_UARTMIS_RXMIS_BITS | UART_UARTMIS_RTMIS_BITS)) {
|
||||
do {
|
||||
serial_rx_byte(UARTx->dr);
|
||||
} while (!(UARTx->fr & UART_UARTFR_RXFE_BITS));
|
||||
} else if (mis & UART_UARTMIS_TXMIS_BITS) {
|
||||
kick_tx();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
serial_enable_tx_irq(void)
|
||||
{
|
||||
if (!(UARTx->fr & UART_UARTFR_TXFF_BITS)) {
|
||||
irqstatus_t flag = irq_save();
|
||||
kick_tx();
|
||||
irq_restore(flag);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
serial_init(void)
|
||||
{
|
||||
enable_pclock(RESETS_RESET_UART0_BITS);
|
||||
|
||||
// Setup baud
|
||||
uint32_t pclk = get_pclock_frequency(RESETS_RESET_UART0_BITS);
|
||||
uint32_t div = DIV_ROUND_CLOSEST(pclk * 4, CONFIG_SERIAL_BAUD);
|
||||
UARTx->ibrd = div >> 6;
|
||||
UARTx->fbrd = div & 0x3f;
|
||||
|
||||
// Enable fifo, set 8N1
|
||||
UARTx->lcr_h = UART_UARTLCR_H_FEN_BITS | UART_UARTLCR_H_WLEN_BITS;
|
||||
UARTx->ifls = 0;
|
||||
UARTx->cr = (UART_UARTCR_RXE_BITS | UART_UARTCR_TXE_BITS
|
||||
| UART_UARTCR_UARTEN_BITS);
|
||||
|
||||
// Setup pins
|
||||
gpio_peripheral(GPIO_Rx, 2, 1);
|
||||
gpio_peripheral(GPIO_Tx, 2, 0);
|
||||
|
||||
// Enable receive irq
|
||||
armcm_enable_irq(UARTx_IRQHandler, UARTx_IRQn, 0);
|
||||
UARTx->imsc = UART_UARTIMSC_RXIM_BITS | UART_UARTIMSC_RTIM_BITS;
|
||||
}
|
||||
DECL_INIT(serial_init);
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
// rp2040 timer support
|
||||
//
|
||||
// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
|
||||
//
|
||||
// This file may be distributed under the terms of the GNU GPLv3 license.
|
||||
|
||||
#include "board/armcm_boot.h" // armcm_enable_irq
|
||||
#include "board/irq.h" // irq_disable
|
||||
#include "board/misc.h" // timer_read_time
|
||||
#include "board/timer_irq.h" // timer_dispatch_many
|
||||
#include "command.h" // DECL_SHUTDOWN
|
||||
#include "hardware/structs/resets.h" // RESETS_RESET_UART0_BITS
|
||||
#include "hardware/structs/timer.h" // RESETS_RESET_UART0_BITS
|
||||
#include "internal.h" // enable_pclock
|
||||
#include "sched.h" // DECL_INIT
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Low level timer code
|
||||
****************************************************************/
|
||||
|
||||
// Return the current time (in absolute clock ticks).
|
||||
uint32_t
|
||||
timer_read_time(void)
|
||||
{
|
||||
return timer_hw->timerawl;
|
||||
}
|
||||
|
||||
static inline void
|
||||
timer_set(uint32_t next)
|
||||
{
|
||||
timer_hw->alarm[0] = next;
|
||||
}
|
||||
|
||||
// Activate timer dispatch as soon as possible
|
||||
void
|
||||
timer_kick(void)
|
||||
{
|
||||
timer_set(timer_read_time() + 50);
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Setup and irqs
|
||||
****************************************************************/
|
||||
|
||||
// Hardware timer IRQ handler - dispatch software timers
|
||||
void __aligned(16)
|
||||
TIMER0_IRQHandler(void)
|
||||
{
|
||||
irq_disable();
|
||||
timer_hw->intr = 1;
|
||||
uint32_t next = timer_dispatch_many();
|
||||
timer_set(next);
|
||||
irq_enable();
|
||||
}
|
||||
|
||||
void
|
||||
timer_init(void)
|
||||
{
|
||||
irq_disable();
|
||||
enable_pclock(RESETS_RESET_TIMER_BITS);
|
||||
timer_hw->timelw = 0;
|
||||
timer_hw->timehw = 0;
|
||||
armcm_enable_irq(TIMER0_IRQHandler, TIMER_IRQ_0_IRQn, 2);
|
||||
timer_hw->inte = 1;
|
||||
timer_kick();
|
||||
irq_enable();
|
||||
}
|
||||
DECL_INIT(timer_init);
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# Base config file for rp2040 boards
|
||||
CONFIG_MACH_RP2040=y
|
||||
Loading…
Reference in New Issue