mirror of https://github.com/Desuuuu/klipper.git
61 lines
4.7 KiB
C
61 lines
4.7 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3XA_SPI1_INSTANCE_
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#define _SAM3XA_SPI1_INSTANCE_
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/* ========== Register definition for SPI1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SPI1_CR (0x4000C000U) /**< \brief (SPI1) Control Register */
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#define REG_SPI1_MR (0x4000C004U) /**< \brief (SPI1) Mode Register */
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#define REG_SPI1_RDR (0x4000C008U) /**< \brief (SPI1) Receive Data Register */
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#define REG_SPI1_TDR (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
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#define REG_SPI1_SR (0x4000C010U) /**< \brief (SPI1) Status Register */
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#define REG_SPI1_IER (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
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#define REG_SPI1_IDR (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
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#define REG_SPI1_IMR (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
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#define REG_SPI1_CSR (0x4000C030U) /**< \brief (SPI1) Chip Select Register */
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#define REG_SPI1_WPMR (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
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#define REG_SPI1_WPSR (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
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#else
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#define REG_SPI1_CR (*(__O uint32_t*)0x4000C000U) /**< \brief (SPI1) Control Register */
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#define REG_SPI1_MR (*(__IO uint32_t*)0x4000C004U) /**< \brief (SPI1) Mode Register */
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#define REG_SPI1_RDR (*(__I uint32_t*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */
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#define REG_SPI1_TDR (*(__O uint32_t*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
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#define REG_SPI1_SR (*(__I uint32_t*)0x4000C010U) /**< \brief (SPI1) Status Register */
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#define REG_SPI1_IER (*(__O uint32_t*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
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#define REG_SPI1_IDR (*(__O uint32_t*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
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#define REG_SPI1_IMR (*(__I uint32_t*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
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#define REG_SPI1_CSR (*(__IO uint32_t*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */
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#define REG_SPI1_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
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#define REG_SPI1_WPSR (*(__I uint32_t*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_SPI1_INSTANCE_ */
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