mirror of https://github.com/Desuuuu/klipper.git
325 lines
16 KiB
C
325 lines
16 KiB
C
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/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : BUSCTRL
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// Version : 1
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// Bus type : apb
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// Description : Register block for busfabric control signals and performance
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// counters
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// =============================================================================
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#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
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#define HARDWARE_REGS_BUSCTRL_DEFINED
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// =============================================================================
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// Register : BUSCTRL_BUS_PRIORITY
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// Description : Set the priority of each master for bus arbitration.
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#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
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#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
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#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_DMA_W
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
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#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
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#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
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#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
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#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_DMA_R
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
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#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
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#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
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#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
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#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_PROC1
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
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#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
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#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
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#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
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#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : BUSCTRL_BUS_PRIORITY_PROC0
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// Description : 0 - low priority, 1 - high priority
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#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
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#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
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#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
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#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
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#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
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// =============================================================================
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// Register : BUSCTRL_BUS_PRIORITY_ACK
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// Description : Bus priority acknowledge
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// Goes to 1 once all arbiters have registered the new global
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// priority levels.
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// Arbiters update their local priority when servicing a new
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// nonsequential access.
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// In normal circumstances this will happen almost immediately.
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#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
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#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
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#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
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#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
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#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
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#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
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// =============================================================================
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// Register : BUSCTRL_PERFCTR0
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// Description : Bus fabric performance counter 0
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// Busfabric saturating performance counter 0
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL0
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#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
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#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
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#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
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#define BUSCTRL_PERFCTR0_MSB _u(23)
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#define BUSCTRL_PERFCTR0_LSB _u(0)
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#define BUSCTRL_PERFCTR0_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL0
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// Description : Bus fabric performance event select for PERFCTR0
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// Select an event for PERFCTR0. Count either contested accesses,
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// or all accesses, on a downstream port of the main crossbar.
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// 0x00 -> apb_contested
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// 0x01 -> apb
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// 0x02 -> fastperi_contested
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// 0x03 -> fastperi
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// 0x04 -> sram5_contested
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// 0x05 -> sram5
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// 0x06 -> sram4_contested
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// 0x07 -> sram4
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// 0x08 -> sram3_contested
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// 0x09 -> sram3
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// 0x0a -> sram2_contested
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// 0x0b -> sram2
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// 0x0c -> sram1_contested
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// 0x0d -> sram1
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// 0x0e -> sram0_contested
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// 0x0f -> sram0
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// 0x10 -> xip_main_contested
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// 0x11 -> xip_main
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// 0x12 -> rom_contested
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// 0x13 -> rom
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#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c)
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#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f)
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#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
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#define BUSCTRL_PERFSEL0_MSB _u(4)
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#define BUSCTRL_PERFSEL0_LSB _u(0)
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#define BUSCTRL_PERFSEL0_ACCESS "RW"
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#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00)
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#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01)
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#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
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#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e)
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#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f)
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#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
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#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11)
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#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12)
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#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13)
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// =============================================================================
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// Register : BUSCTRL_PERFCTR1
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// Description : Bus fabric performance counter 1
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// Busfabric saturating performance counter 1
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL1
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#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
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#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
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#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
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#define BUSCTRL_PERFCTR1_MSB _u(23)
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#define BUSCTRL_PERFCTR1_LSB _u(0)
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#define BUSCTRL_PERFCTR1_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL1
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// Description : Bus fabric performance event select for PERFCTR1
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// Select an event for PERFCTR1. Count either contested accesses,
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// or all accesses, on a downstream port of the main crossbar.
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// 0x00 -> apb_contested
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// 0x01 -> apb
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// 0x02 -> fastperi_contested
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// 0x03 -> fastperi
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// 0x04 -> sram5_contested
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// 0x05 -> sram5
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// 0x06 -> sram4_contested
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// 0x07 -> sram4
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// 0x08 -> sram3_contested
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// 0x09 -> sram3
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// 0x0a -> sram2_contested
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// 0x0b -> sram2
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// 0x0c -> sram1_contested
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// 0x0d -> sram1
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// 0x0e -> sram0_contested
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// 0x0f -> sram0
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// 0x10 -> xip_main_contested
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// 0x11 -> xip_main
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// 0x12 -> rom_contested
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// 0x13 -> rom
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#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014)
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#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f)
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#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
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#define BUSCTRL_PERFSEL1_MSB _u(4)
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#define BUSCTRL_PERFSEL1_LSB _u(0)
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#define BUSCTRL_PERFSEL1_ACCESS "RW"
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#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00)
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#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01)
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#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
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#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e)
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#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f)
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#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
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#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11)
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#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12)
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#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13)
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// =============================================================================
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// Register : BUSCTRL_PERFCTR2
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// Description : Bus fabric performance counter 2
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// Busfabric saturating performance counter 2
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL2
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#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
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#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
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#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
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#define BUSCTRL_PERFCTR2_MSB _u(23)
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#define BUSCTRL_PERFCTR2_LSB _u(0)
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#define BUSCTRL_PERFCTR2_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL2
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// Description : Bus fabric performance event select for PERFCTR2
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// Select an event for PERFCTR2. Count either contested accesses,
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// or all accesses, on a downstream port of the main crossbar.
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// 0x00 -> apb_contested
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// 0x01 -> apb
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// 0x02 -> fastperi_contested
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// 0x03 -> fastperi
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// 0x04 -> sram5_contested
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// 0x05 -> sram5
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// 0x06 -> sram4_contested
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// 0x07 -> sram4
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// 0x08 -> sram3_contested
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// 0x09 -> sram3
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// 0x0a -> sram2_contested
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// 0x0b -> sram2
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// 0x0c -> sram1_contested
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// 0x0d -> sram1
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// 0x0e -> sram0_contested
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// 0x0f -> sram0
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// 0x10 -> xip_main_contested
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// 0x11 -> xip_main
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// 0x12 -> rom_contested
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// 0x13 -> rom
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#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c)
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#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f)
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#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
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#define BUSCTRL_PERFSEL2_MSB _u(4)
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#define BUSCTRL_PERFSEL2_LSB _u(0)
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#define BUSCTRL_PERFSEL2_ACCESS "RW"
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#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00)
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#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01)
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#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
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#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e)
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#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f)
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#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
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#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11)
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#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12)
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#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13)
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// =============================================================================
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// Register : BUSCTRL_PERFCTR3
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// Description : Bus fabric performance counter 3
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// Busfabric saturating performance counter 3
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// Count some event signal from the busfabric arbiters.
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// Write any value to clear. Select an event to count using
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// PERFSEL3
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#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
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#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
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#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
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#define BUSCTRL_PERFCTR3_MSB _u(23)
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#define BUSCTRL_PERFCTR3_LSB _u(0)
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#define BUSCTRL_PERFCTR3_ACCESS "WC"
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// =============================================================================
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// Register : BUSCTRL_PERFSEL3
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// Description : Bus fabric performance event select for PERFCTR3
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// Select an event for PERFCTR3. Count either contested accesses,
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// or all accesses, on a downstream port of the main crossbar.
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// 0x00 -> apb_contested
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// 0x01 -> apb
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// 0x02 -> fastperi_contested
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// 0x03 -> fastperi
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// 0x04 -> sram5_contested
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||
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// 0x05 -> sram5
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||
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// 0x06 -> sram4_contested
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||
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// 0x07 -> sram4
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||
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// 0x08 -> sram3_contested
|
||
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// 0x09 -> sram3
|
||
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// 0x0a -> sram2_contested
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||
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// 0x0b -> sram2
|
||
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// 0x0c -> sram1_contested
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||
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// 0x0d -> sram1
|
||
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// 0x0e -> sram0_contested
|
||
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// 0x0f -> sram0
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||
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// 0x10 -> xip_main_contested
|
||
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// 0x11 -> xip_main
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||
|
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// 0x12 -> rom_contested
|
||
|
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// 0x13 -> rom
|
||
|
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#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024)
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||
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#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f)
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||
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#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
|
||
|
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#define BUSCTRL_PERFSEL3_MSB _u(4)
|
||
|
|
#define BUSCTRL_PERFSEL3_LSB _u(0)
|
||
|
|
#define BUSCTRL_PERFSEL3_ACCESS "RW"
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
|
||
|
|
#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
|
||
|
|
// =============================================================================
|
||
|
|
#endif // HARDWARE_REGS_BUSCTRL_DEFINED
|