mirror of https://github.com/Desuuuu/klipper.git
110 lines
8.0 KiB
C
110 lines
8.0 KiB
C
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/*************************************************************************//**
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* @file RP2040.h
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* @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
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* Device RP2040
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* @version V1.0.0
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* @date 5. May 2021
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*****************************************************************************/
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/*
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _CMSIS_RP2040_H_
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#define _CMSIS_RP2040_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* =========================================================================================================================== */
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/* ================ Interrupt Number Definition ================ */
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/* =========================================================================================================================== */
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typedef enum
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{
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/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */
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Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
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SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
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PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
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SysTick_IRQn = -1, /*!< -1 System Tick Timer */
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/* =========================================== RP2040 Specific Interrupt Numbers =========================================== */
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TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */
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TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */
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TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */
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TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */
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PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */
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USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */
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XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */
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PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */
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PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */
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PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */
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PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */
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DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */
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DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */
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IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */
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IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */
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SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */
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SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */
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CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */
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SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */
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SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */
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UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */
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UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */
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ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */
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I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */
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I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */
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RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */
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} IRQn_Type;
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/* =========================================================================================================================== */
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/* ================ Processor and Core Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */
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#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
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#define __MPU_PRESENT 1 /*!< MPU present */
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#define __FPU_PRESENT 0 /*!< FPU present */
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/** @} */ /* End of group Configuration_of_CMSIS */
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#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
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#include "system_RP2040.h" /*!< RP2040 System */
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#ifndef __IM /*!< Fallback for older CMSIS versions */
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#define __IM __I
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#endif
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#ifndef __OM /*!< Fallback for older CMSIS versions */
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#define __OM __O
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#endif
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#ifndef __IOM /*!< Fallback for older CMSIS versions */
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#define __IOM __IO
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CMSIS_RP2040_H */
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