mirror of https://github.com/Desuuuu/klipper.git
81 lines
6.7 KiB
C
81 lines
6.7 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4S_SPI_INSTANCE_
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#define _SAM4S_SPI_INSTANCE_
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/* ========== Register definition for SPI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */
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#define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */
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#define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */
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#define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
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#define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */
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#define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
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#define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
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#define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
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#define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */
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#define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Mode Register */
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#define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
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#define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
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#define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */
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#define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
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#define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
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#define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
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#define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
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#define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
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#define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
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#define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */
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#define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */
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#else
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#define REG_SPI_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI) Control Register */
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#define REG_SPI_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI) Mode Register */
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#define REG_SPI_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI) Receive Data Register */
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#define REG_SPI_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
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#define REG_SPI_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI) Status Register */
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#define REG_SPI_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
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#define REG_SPI_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
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#define REG_SPI_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
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#define REG_SPI_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI) Chip Select Register */
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#define REG_SPI_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI) Write Protection Mode Register */
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#define REG_SPI_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
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#define REG_SPI_RPR (*(__IO uint32_t*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
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#define REG_SPI_RCR (*(__IO uint32_t*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
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#define REG_SPI_TPR (*(__IO uint32_t*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
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#define REG_SPI_TCR (*(__IO uint32_t*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
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#define REG_SPI_RNPR (*(__IO uint32_t*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
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#define REG_SPI_RNCR (*(__IO uint32_t*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
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#define REG_SPI_TNPR (*(__IO uint32_t*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
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#define REG_SPI_TNCR (*(__IO uint32_t*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
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#define REG_SPI_PTCR (*(__O uint32_t*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
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#define REG_SPI_PTSR (*(__I uint32_t*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4S_SPI_INSTANCE_ */
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