mirror of https://github.com/Desuuuu/klipper.git
190 lines
14 KiB
C
190 lines
14 KiB
C
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/**
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* \file
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*
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* \brief Component description for RSTC
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_RSTC_COMPONENT_H_
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#define _SAME70_RSTC_COMPONENT_H_
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#define _SAME70_RSTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
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/** \addtogroup SAME_SAME70 Reset Controller
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* @{
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*/
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR RSTC */
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/* ========================================================================== */
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#ifndef COMPONENT_TYPEDEF_STYLE
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#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
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#endif
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#define RSTC_11009 /**< (RSTC) Module ID */
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#define REV_RSTC N /**< (RSTC) Module revision */
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/* -------- RSTC_CR : (RSTC Offset: 0x00) (/W 32) Control Register -------- */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'N'
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typedef union {
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struct {
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uint32_t PROCRST:1; /**< bit: 0 Processor Reset */
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uint32_t :2; /**< bit: 1..2 Reserved */
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uint32_t EXTRST:1; /**< bit: 3 External Reset */
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uint32_t :20; /**< bit: 4..23 Reserved */
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uint32_t KEY:8; /**< bit: 24..31 System Reset Key */
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} bit; /**< Structure used for bit access */
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uint32_t reg; /**< Type used for register access */
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} RSTC_CR_Type;
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#endif
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RSTC_CR_OFFSET (0x00) /**< (RSTC_CR) Control Register Offset */
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#define RSTC_CR_PROCRST_Pos 0 /**< (RSTC_CR) Processor Reset Position */
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#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */
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#define RSTC_CR_PROCRST RSTC_CR_PROCRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_PROCRST_Msk instead */
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#define RSTC_CR_EXTRST_Pos 3 /**< (RSTC_CR) External Reset Position */
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#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */
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#define RSTC_CR_EXTRST RSTC_CR_EXTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_EXTRST_Msk instead */
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#define RSTC_CR_KEY_Pos 24 /**< (RSTC_CR) System Reset Key Position */
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#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */
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#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))
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#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */
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#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */
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#define RSTC_CR_MASK _U_(0xFF000009) /**< \deprecated (RSTC_CR) Register MASK (Use RSTC_CR_Msk instead) */
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#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */
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/* -------- RSTC_SR : (RSTC Offset: 0x04) (R/ 32) Status Register -------- */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'N'
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typedef union {
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struct {
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uint32_t URSTS:1; /**< bit: 0 User Reset Status */
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uint32_t :7; /**< bit: 1..7 Reserved */
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uint32_t RSTTYP:3; /**< bit: 8..10 Reset Type */
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uint32_t :5; /**< bit: 11..15 Reserved */
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uint32_t NRSTL:1; /**< bit: 16 NRST Pin Level */
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uint32_t SRCMP:1; /**< bit: 17 Software Reset Command in Progress */
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uint32_t :14; /**< bit: 18..31 Reserved */
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} bit; /**< Structure used for bit access */
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uint32_t reg; /**< Type used for register access */
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} RSTC_SR_Type;
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#endif
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RSTC_SR_OFFSET (0x04) /**< (RSTC_SR) Status Register Offset */
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#define RSTC_SR_URSTS_Pos 0 /**< (RSTC_SR) User Reset Status Position */
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#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */
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#define RSTC_SR_URSTS RSTC_SR_URSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_URSTS_Msk instead */
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#define RSTC_SR_RSTTYP_Pos 8 /**< (RSTC_SR) Reset Type Position */
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#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */
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#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos))
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#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */
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#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */
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#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */
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#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */
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#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */
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#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */
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#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */
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#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */
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#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */
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#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */
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#define RSTC_SR_NRSTL_Pos 16 /**< (RSTC_SR) NRST Pin Level Position */
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#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */
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#define RSTC_SR_NRSTL RSTC_SR_NRSTL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_NRSTL_Msk instead */
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#define RSTC_SR_SRCMP_Pos 17 /**< (RSTC_SR) Software Reset Command in Progress Position */
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#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */
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#define RSTC_SR_SRCMP RSTC_SR_SRCMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_SRCMP_Msk instead */
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#define RSTC_SR_MASK _U_(0x30701) /**< \deprecated (RSTC_SR) Register MASK (Use RSTC_SR_Msk instead) */
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#define RSTC_SR_Msk _U_(0x30701) /**< (RSTC_SR) Register Mask */
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/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'N'
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typedef union {
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struct {
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uint32_t URSTEN:1; /**< bit: 0 User Reset Enable */
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uint32_t :3; /**< bit: 1..3 Reserved */
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uint32_t URSTIEN:1; /**< bit: 4 User Reset Interrupt Enable */
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uint32_t :3; /**< bit: 5..7 Reserved */
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uint32_t ERSTL:4; /**< bit: 8..11 External Reset Length */
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uint32_t :12; /**< bit: 12..23 Reserved */
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uint32_t KEY:8; /**< bit: 24..31 Write Access Password */
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} bit; /**< Structure used for bit access */
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uint32_t reg; /**< Type used for register access */
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} RSTC_MR_Type;
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#endif
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RSTC_MR_OFFSET (0x08) /**< (RSTC_MR) Mode Register Offset */
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#define RSTC_MR_URSTEN_Pos 0 /**< (RSTC_MR) User Reset Enable Position */
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#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */
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#define RSTC_MR_URSTEN RSTC_MR_URSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTEN_Msk instead */
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#define RSTC_MR_URSTIEN_Pos 4 /**< (RSTC_MR) User Reset Interrupt Enable Position */
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#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */
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#define RSTC_MR_URSTIEN RSTC_MR_URSTIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTIEN_Msk instead */
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#define RSTC_MR_ERSTL_Pos 8 /**< (RSTC_MR) External Reset Length Position */
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#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */
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#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))
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#define RSTC_MR_KEY_Pos 24 /**< (RSTC_MR) Write Access Password Position */
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#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */
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#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))
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#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
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#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
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#define RSTC_MR_MASK _U_(0xFF000F11) /**< \deprecated (RSTC_MR) Register MASK (Use RSTC_MR_Msk instead) */
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#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'R'
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/** \brief RSTC hardware registers */
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typedef struct {
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__O uint32_t RSTC_CR; /**< (RSTC Offset: 0x00) Control Register */
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__I uint32_t RSTC_SR; /**< (RSTC Offset: 0x04) Status Register */
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__IO uint32_t RSTC_MR; /**< (RSTC Offset: 0x08) Mode Register */
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} Rstc;
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#elif COMPONENT_TYPEDEF_STYLE == 'N'
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/** \brief RSTC hardware registers */
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typedef struct {
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__O RSTC_CR_Type RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
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__I RSTC_SR_Type RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */
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__IO RSTC_MR_Type RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */
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} Rstc;
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#else /* COMPONENT_TYPEDEF_STYLE */
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#error Unknown component typedef style
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#endif /* COMPONENT_TYPEDEF_STYLE */
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/** @} end of Reset Controller */
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#endif /* _SAME70_RSTC_COMPONENT_H_ */
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